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This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper investigates the formation control problem for linear multi-agent systems under switching directed topologies. Based on absolute or relative outputs, we propose two distributed observer-based event-triggered control schemes. Both schemes can guarantee the boundedness of formation errors under sufficient conditions. The schemes can also avoid Zeno behaviors by giving an estimation for the lower bound of sampling intervals. Finally, simulations and experiments validate the proposed approaches. [ABSTRACT FROM AUTHOR]

This paper addresses the finite-time and fixed-time bipartite average tracking (BAT) problems in multi-agent systems (MASs) subject to bounded disturbances. A novel non-smooth protocol is first constructed on the basis of utilizing the finite-time control method, which can realize the finite-time BAT with structurally balanced graph. Then, the fixed-time BAT problem is dealt with nonlinear fixed-time algorithm, the setting time of which is obtained without depending on initial states. By employing Lyapunov stability theory, some sufficient criteria are obtained to achieve the finite-time and fixed-time BAT for MASs with disturbances. Numerical examples are finally developed for illustration. [ABSTRACT FROM AUTHOR]

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $. In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively. [ABSTRACT FROM AUTHOR]

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a novel distributed fault-tolerant consensus tracking control design for multi-agent systems with abrupt and incipient actuator faults under fixed and switching topologies. The fault and state information of each individual agent is estimated by merging unknown input observer in the decentralized fault estimation hierarchy. Then, two kinds of distributed fault-tolerant consensus tracking control schemes with average dwelling time technique are developed to guarantee the mean-square exponential consensus convergence of multi-agent systems, respectively, on the basis of the relative neighboring output information as well as the estimated information in fault estimation. Simulation results demonstrate the effectiveness of the proposed fault-tolerant consensus tracking control algorithm. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR. [ABSTRACT FROM AUTHOR]

This paper addresses the consensus problem for two-layered MASs (multi-agent systems) subject to attacks on communication edges. Unlike most existing two-layered MAS models, the considered MASs are allowed to have heterogeneous inner communication topologies between the different layers. By using the linear transformation technique, some sufficient criteria are first given to achieve consensus among the leaders within the leader layer where the condition that the interaction topology has directed spanning trees with a fixed root required in most existing works has been removed. Furthermore, based on the relative outputs, observer-based controllers are designed to achieve node-to-node consensus among the two layers. By developing a new kind of multiple Lyapunov function (MLF) based on a bisection search method, some criteria are established under which the node-to-node consensus error will converge into a bounded set asymptotically. It is interestingly found that a less conservative average dwell time (ADT) constraint is obtained for achieving node-to-node consensus by utilizing the proposed MLF compared with that yielded by the traditional MLF constructed from nonsingular $M$ matrix theory. Moreover, we show that consensus can be achieved asymptotically in the layered MASs with the same inner topology subject to synchronous attacks under some suitable conditions. Finally, the effectiveness of the criteria is verified by simulation on networking linear oscillators. [ABSTRACT FROM AUTHOR]

The current paper investigates energy-constraint formation design and analysis problems for multiagent systems with two types of switching interaction topologies; that is, leaderless ones and leader-following ones. Firstly, a new formation control protocol with switching interaction topologies is shown, where the whole energy supply is limited previously. Then, by constructing the relationship of the whole energy supply and the matrix variable, sufficient conditions for leaderless energy-constraint formation design and analysis are respectively presented by the linear matrix inequality tool. Furthermore, an approach is proposed to determine an explicit expression of the formation center function, which determines the macroscopic motion of a multiagent system as a whole and consists of two parts: the initial state term and the formation function term. Moreover, main conclusions of leaderless energy-constraint formation are extended into leader-following multiagent systems by a new two-step transformation approach, where the asymmetric structure feature of leader-following switching interaction topologies is well dealt with. Finally, two numerical examples are provided to demonstrate the effectiveness of main conclusions. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper proposes an SST-CML-Hybrid (SCH) output driver, and its corresponding hybrid-path feed-forward equalization (FFE) scheme, to enhance the energy efficiency of a PAM-4 transmitter (TX). Specifically, the SCH driver features one SST branch + one CML branch to co-synthesize the PAM-4 data, reducing substantially the signaling power, switching power and equalization power. The PAM-4 TX further integrates a half-rate serializer with 4-bit 3-tap FFE, duty-cycle correction circuits and a T-coil output matching network. Prototyped in 28-nm CMOS, the PAM-4 TX achieves a broadband return loss <−10dB up to 50 GHz, and occupies a compact die area of 0.0345 mm2. Operating at 40 Gb/s and at a 0.9-V supply, the TX dissipates 19.5 mW, of which 6.4 mW is due to the SCH driver. The corresponding energy efficiencies are 0.16 and 0.5 pJ/bit for the SCH driver and TX, respectively; both compare favorably with the prior art. [ABSTRACT FROM AUTHOR]

In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58% when the charger operates in the turbo boost mode, and achieves 97% maximum efficiency when the charger operates in buck charge mode. [ABSTRACT FROM AUTHOR]

The recently-proposed dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is a promising approach for enabling the implementation of multiple fully-integrated power supplies with superior dynamic and cross-regulation performance in SoCs. However, switching the input and output stages at different frequencies raises many questions about the optimum strategy for controlling such converter topology. This paper explores and analyzes the various classes of controllers that can be employed in the output stage of the DF-SIMO buck converter topology, while taking account of key comparison metrics, such as circuit complexity, stability, steady-state and dynamic performance, and the range of operating conditions each controller may be suitable for. This includes average-based voltage-mode, ripple-based charge-mode, and ripple-based voltage-mode controllers. The predictions made by the analytical expressions derived for the various controllers are verified through system-level and transistor-level circuit simulations. [ABSTRACT FROM AUTHOR]

Low-power circuits often employ dynamic voltage scaling and energy harvesting. Such circuits need a power management unit that can convert the voltage source to a wide range of target voltages with high efficiency. Targeting such a power management unit, this paper presents a reconfigurable architecture of switched capacitor (SC) voltage converter. It introduces a design optimization methodology that can determine trade-off among design parameters to meet the goal. The proposed converter employs a reconfigurable topology with four capacitors. It provides 11 conversion ratios: 6 step-down and 5 step-up ratios supporting wide input/output voltage range. An analytical model for the output impedance of the proposed reconfigurable SC topology is presented. Using the model, the proposed optimization methodology can minimize the total power dissipation. To validate the proposed architecture and optimization methodology, the converter has been implemented in a 130-nm CMOS process using integrated capacitors of total size 2.2 nF. Simulation results show that the optimized converter circuit achieves an efficiency range from 83.41% to 74.69% for a load current of $100~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper is concerned with an observer-based distributed secure consensus control strategy for a class of linear multi-agent systems (MASs) with random attacks. Due to the fact that not all state information is available, observers are employed to estimate the internal states. The communication topology is randomly switching under the attacks, and a distributed secure consensus strategy is proposed using the output information. The feedback gains are calculated via solving the Riccati equation and Riccati inequality, and stability analysis is proven that the MAS achieves secure consensus tracking in the mean square sense. Finally, two examples are provided to verify the effectiveness of the observer-based control strategy. [ABSTRACT FROM AUTHOR]

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth-order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure-of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst additionally offering direct integration with digital systems. [ABSTRACT FROM AUTHOR]

Considering the coupling relationships between transfer power and efficiency in continuous-mode inductive power transfer (IPT) systems, this paper presents a pulse energy injection inverter for IPT systems. With a new topology and parameters tuning, the pulse energy injection IPT system with the proposed inverter can work in switch-mode to decouple transfer power with efficiency. Moreover, the transfer power is only decided by the duty ratio of the semiconductor switch, rather than affected by the transmitting resonator, receiving (Rx) resonator, and load. In this way, the pulse energy injection IPT system holds an operating frequency much lower than the resonant frequency to reduce switch loss and improve transfer efficiency. Experiments verify that the IPT system with proposed inverter maintains a high level efficiency within the middle range and realizes nearly 80% supply to load transfer efficiency even in a weak coupling coefficient ( $k=0.044$ ). Finally, experimental analysis implies that the pulse energy injection inverter is suitable for full-range transmission, and high-Q IPT systems with uncertainty in Rx circuits or load. [ABSTRACT FROM AUTHOR]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

The instrumentation systems for implantable brain–machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a $\Delta \Sigma $ SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0–2MASH topology. This configuration uses a specialized FIR window to decimate the $\Delta \Sigma $ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using $0.18\,\mu $ m CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm2 silicon footprint. Moreover, a 14fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications. [ABSTRACT FROM PUBLISHER]

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices. Due to the significant power consumption in the multiplier components of the FIR filter, various techniques aimed at reducing the switching activity of these multipliers have been proposed in the literature. However, these techniques rarely exploit the flexibility on the algorithmic level, which can lead to additional benefits. In this paper, FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime, while ensuring the full baseline performance of any programmed filter whenever it is required. The analyzed FIR filters were fabricated in a 28nm FD-SOI test chip and measured at a near-threshold, 600mV supply voltage. For example, by carefully choosing slightly perturbed coefficients in a low-pass configuration, power savings of up to 33% are achieved when accepting a 3dB degradation on the stopband, as compared with the baseline implementation of the filter. [ABSTRACT FROM PUBLISHER]

This paper investigates the event-triggering containment control of multi-agent networks with fixed and switching topologies, where there exist interactions between the leaders. Two cases are studied, respectively: One is that the leaders are opinionated. Then each leader will converge to its initial goal and the followers converge to the convex hull formed by the leaders. The other is that the leaders are not opinionated. Then the leaders will not insist on their initial goals and converge to some compromising states due to the interactions among them, while the followers still converge to the convex hull formed by the leaders. By means of pull-based event-triggering control, the event-triggering containment control problems of multi-agent systems with fixed and switching topologies are investigated, respectively. Finally, simulations are given to illustrate the theoretical results. [ABSTRACT FROM AUTHOR]

In this paper, the controllability problem is addressed for temporally switching networks and the associated temporally switching systems. The state controllability criterion of temporally switching systems is firstly obtained, which stands for structural controllability of temporally switching networks with the same structure. With a new temporal interpretation of the dilation and intersection concepts, some algebraic and graphic criteria are precisely derived. Specifically, it reveals that the essence for the structural controllability is the existence of $n$ temporally independent walks (the $n$-walk theory), which generalizes the classical concept of cactus in graph theory to temporal networks. Furthermore, from the perspective of the new $n$-walk theory, its uniqueness makes the notion of strong structural controllability more precise and clearer for temporal networks. This comprehension of the (strong) structural controllability concept not only is of particular advantage for more in-depth studies of network control problems, but also provides useful guidance for constructing controllable temporal networks. [ABSTRACT FROM PUBLISHER]

A pair of universal current mode control schemes for charging a Li-ion battery for mobile applications are discussed in this paper. The peak-current mode control schemes, based on a single control loop, is universal because it is designed with a single-stage buck charger for both a conventional wall adapter dc source as well as a solar photovoltaic (PV) module of comparable specifications. The charging schemes remove the need for an extra MPPT (maximum power point tracking) power converter stage. This control scheme is non-linear and incorporates all possible scenarios: mode of operation of a battery, current charging rate and power characteristic of input source. The algorithm uses need-based MPPT and ensures minimal battery discharge, and also uses minimum number of sense variables in the circuit. The methods differ in the way MPPT is implemented: perturb and observe (P&O) and fractional open circuit voltage. Simulation results demonstrating battery charge profile, validity of the algorithm under varying insolation conditions and platform workloads are presented, along with a discussion of the trade-offs of the two methods. Proof-of-concept hardware results are also provided. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based on general transposed series parallel (GTSP) topology, is studied and the losses are calculated, which in turn enables the “bottlenecks” to be identified and overcome. The calculations show that for a given number of switching cells the power losses of such converters are mainly dependent on the voltage conversion ratio, the topology function, the resistances of the switches in on and off states, the ESR of the capacitors, the switching frequency, the voltage drop, and the load. The theory explains the fact that was observed in experiments, that for low voltage conversion ratio values, efficiency decrease was measured. It is shown that for these low voltage ratio values the mechanism associated to the off resistance of the switches is more dominant and reduces the efficiency. This power loss estimation can be used as a powerful tool for the performance optimization of capacitive converters. The theoretical results are verified experimentally on a 10-cell GTSP converter prototype. The experimental results show good agreement with the proposed theory. [ABSTRACT FROM PUBLISHER]

This paper studies asymptotic output synchronization for a class of dynamical networks with identical nonlinear nodes and switching topology. The node dynamics are characterized by a quadratic form of incremental-dissipativity. The output synchronization problem of the switched network is first converted into the set stability problem for the interconnected nonlinear system with a particular selection of input-output pair, which preserves dissipativity. Then, synchronization under arbitrary switching among self-synchronizing subnetworks and synchronization by design of switching among subnetworks, where none of them is necessarily self-synchronizing, are investigated by using the common Lyapunov function method and the single Lyapunov function method, respectively. Algebraic synchronization criteria for both cases are established, and the obtained results are applied to the investigation of coupled biochemical oscillators and coupled Chua's circuits. [ABSTRACT FROM AUTHOR]

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency (>80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA. [ABSTRACT FROM AUTHOR]

This article presents a compact integrated receiver front-end for phased-arrays at 5G n257/n261 band (26.5–29.5 GHz) employing both a low-noise amplifier (LNA) and a novel passive phase-shifter based on variable-phase all-pass networks. The proposed phase-shifter topology is analysed and designed using 0.25 μm BiCMOS achieving continuous tuning capabilities with 360° phase range over a 25–33 GHz frequency range under 0.1 mm2 of area. The proposed phase-shifter is measured standalone, achieving 8.3 ± 0.55 dB losses at 29 GHz with an RMS gain error below 0.6 dB across the entire frequency range. When quantizing the continuous phase-shift into 6 bits, an RMS phase error < 3° is obtained. To build the LNA-Phase-shifter combo, the phase-shifter is then integrated with an LNA optimized for compactness, which was measured standalone, showing a noise figure below 3.2 dB across the n257/n261 band and 20 dB gain under 0.0625 mm2 of area. The small size of both the phase-shifter and LNA enables an ultra-compact phased-array receiver front-end under 0.2 mm2 of area. The front-end is measured, achieving 11.5 ± 0.53 dB of gain, RMS gain error below 0.42 dB and RMS phase error below 3.2° over the entire n257 band, measured input-referred P1dB of −25 dBm and a 15 mW DC power consumption. [ABSTRACT FROM AUTHOR]

A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13- $\mu \text{m}$ CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150- $\mu \text{W}$ power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm2. The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters. [ABSTRACT FROM AUTHOR]

The evolution of the target system (leader) in pinning-controlled complex networks may need to be regulated by some control inputs for performing various practical tasks, e.g., obstacle avoidance, tracking highly maneuverable target, and so on. Motivated by this observation, we shall investigate the global pinning synchronization problems for complex switching networks for which the target system is subject to nonzero control inputs. First, using the idea of unit vector function method, a discontinuous coupling law is designed. With the aid of stability theory for switched systems, it is theoretically shown that synchronization in the network under this discontinuous coupling law can be achieved by choosing sufficiently large coupling strengths if the average dwell time (ADT) is bounded below by a positive constant. Second, we use the boundary layer method to design a continuous-coupling law. It has been theoretically shown that the synchronization error is ultimately uniformly bounded (UUB) under this continuous-coupling law. The chattering effect is also avoided in real implementation by using this continuous-coupling law. Furthermore, for networks with unknown external disturbances and unmodeled dynamics, neuro-adaptive-based coupling laws are designed to ensure that the synchronization error of the networks with undirected switching communication topologies under these laws is UUB. The obtained theoretical results are finally validated by performing numerical simulation on coupling Chua’s circuit systems. [ABSTRACT FROM AUTHOR]

Multi-layer networks, which incorporate multiple subsystems and different kinds of interactions, are recently believed to have a stronger ability in modelling various real-world systems than traditional single-layer complex networks. Motivated by this observation, we try to show how to achieve node-to-node synchronization and complete synchronization in multi-layer networks under directed switching communication topologies, where the nodes have Lur’e type dynamics. First, by using the multiple Lyapunov stability theory, we show that node-to-node synchronization in two-layer networks can be achieved by choosing sufficiently large coupling strength as well as suitable feedback gain matrix if the average dwell time is bounded below by some positive constants. The result is then extended to the case of multiple layers. Furthermore, if the inner communication topologies of each layer have a directed spanning tree with a common root, we show complete synchronization in the considered network can be achieved if the control parameters and the average dwell time are appropriately chosen. Finally, the theoretical results are validated through performing numerical simulations on Chua’s circuit with double scroll attractors. [ABSTRACT FROM AUTHOR]

To reduce actuation burden in dynamical network environment, the event-triggering strategy is applied to consensus protocol for a class of nonlinear multi-agent systems with a switching topology. The considered switching topology is assumed to be sequentially connected, which is directed disconnected. The combinational measurement approach is adopted in the event-triggering strategy such that each agent updates control rule only at its own event-triggering instants. First, by using the iterative method, we establish the recursive relationship of maximal distance sequence. Then, sufficient conditions of event-based bounded consensus can be obtained by the contractive property of maximal distance sequence. Meanwhile, it is proved that the designed event-triggering rule can avoid Zeno behavior. Furthermore, as an extension, we consider the case of jointly connected topology, and the corresponding consensus problem is also explored. Finally, a numerical simulation is provided to confirm the derived theoretical results. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of $89~\mu $ Vrms, and reliable sensing of signal level of 1 mV. [ABSTRACT FROM AUTHOR]

An integrated feedback controlled class E coil driver for wirelessly powering biomedical implants was implemented in a high voltage 0.18 \mum CMOS process. The coil driver was compensated using a discrete switched-capacitor controller for reducing the compensation capacitor area. A linearized discrete-time model was also developed for analyzing the stability of the proposed coil driver. Different methods to reduce the on-resistance of the coil driver switch had also been investigated. When compared to the previous design, the figure of merit for measuring the effectiveness of generating coil current was improved over 2.5 times. ASK modulation on the coil current was achieved by switching on or off an additional off-chip capacitor. Power increase during ASK modulation was reduced by 49.4% when compared to the previous design. [ABSTRACT FROM AUTHOR]