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This paper deals with nonlinear control of a single-phase half-bridge interleaved buck shunt active power filter (HBIB-SAPF) with a nonlinear load. The control objective for the system is twofold: performing power factor correction by compensating for harmonics and reactive current consumed by the nonlinear load from one hand and tightly regulating the HBIB converter DC capacitor voltage. Both objectives are accomplished using a two-loop nonlinear controller. The inner loop acts on the switching devices so that the active filter current tracks its reference with the aim of ensuring a unity power factor. This loop is tackled using backstepping technique and Lyapunov approach. The outer loop is responsible for regulating the DC capacitor voltage to its desired value, using a PI controller with a pre-filter. The stability analysis of the closed-loop system is formally performed by using the averaging theory. The validity of the designed nonlinear controller is checked by simulations in Matlab/SimpowerSystem showing its robustness and accuracy under various operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new scheme to directly power a 4.9–5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3–2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/ $\sqrt {\mathrm{ Hz}}$ , which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65dBc under the 30mVpp ripple of the converter. [ABSTRACT FROM AUTHOR]

This paper introduces a fully integrated switched-capacitor (SC) DC-DC boost converter suitable for energy harvesting in miniature sensor systems with varying harvesting source and battery voltages. Unlike the conventional SC DC-DC boost converters, where efficiency is optimized only for a few topology-dependent voltage conversion ratios (VCRs), the proposed soft-charging-based SC converter achieved VCR-insensitive evenly high efficiency for a wide range of input and output voltages. A test chip was fabricated in 180nm process, and the measured peak efficiency and average efficiency are 85.3% and 83.6%, respectively, for 1.8V regulated output voltage and a wide range of input voltages (0.95–1.8 V). Also, a peak efficiency of 88.9% and average efficiency of 87.6% are achieved for a wide range of battery output voltages (3.0–4.2 V) and a 1.2V harvesting source input voltage. [ABSTRACT FROM AUTHOR]

This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR. [ABSTRACT FROM AUTHOR]

This paper proposes a LLC type resonant forward converter using adjustable turning-off time control for low power and voltage applications. The new circuit is derived from the conventional LLC converter, and it has simple structure while maintaining decent soft-switching characteristics. The switching losses are reduced by ZVS (zero voltage switching) and ZCS (zero current switching). Also, regulation of the output voltage does not require a small ratio between magnetizing inductor and resonant inductor, so the leakage inductor of transformer can be utilized instead of an external inductor to realize resonance, which makes it possible to use only one magnetic component in the resonant topology. Besides, the adjustable turning-off time control strategy is adopted in the scheme, which optimizes the switching condition while ensuring the wide range operation. In comparison to the traditional PWM (pulse width modulation) control, the proposed control strategy can further reduce the switching loss and improve power efficiency. This is also suitable for the utilization of GaN (gallium nitride) devices due to the requirement of higher switching frequencies at wide input applications. In addition to the detailed theoretical analysis, the validity of the proposed concept is confirmed by the experimental results of a prototype. [ABSTRACT FROM AUTHOR]

In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58% when the charger operates in the turbo boost mode, and achieves 97% maximum efficiency when the charger operates in buck charge mode. [ABSTRACT FROM AUTHOR]

The recently-proposed dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is a promising approach for enabling the implementation of multiple fully-integrated power supplies with superior dynamic and cross-regulation performance in SoCs. However, switching the input and output stages at different frequencies raises many questions about the optimum strategy for controlling such converter topology. This paper explores and analyzes the various classes of controllers that can be employed in the output stage of the DF-SIMO buck converter topology, while taking account of key comparison metrics, such as circuit complexity, stability, steady-state and dynamic performance, and the range of operating conditions each controller may be suitable for. This includes average-based voltage-mode, ripple-based charge-mode, and ripple-based voltage-mode controllers. The predictions made by the analytical expressions derived for the various controllers are verified through system-level and transistor-level circuit simulations. [ABSTRACT FROM AUTHOR]

Low-power circuits often employ dynamic voltage scaling and energy harvesting. Such circuits need a power management unit that can convert the voltage source to a wide range of target voltages with high efficiency. Targeting such a power management unit, this paper presents a reconfigurable architecture of switched capacitor (SC) voltage converter. It introduces a design optimization methodology that can determine trade-off among design parameters to meet the goal. The proposed converter employs a reconfigurable topology with four capacitors. It provides 11 conversion ratios: 6 step-down and 5 step-up ratios supporting wide input/output voltage range. An analytical model for the output impedance of the proposed reconfigurable SC topology is presented. Using the model, the proposed optimization methodology can minimize the total power dissipation. To validate the proposed architecture and optimization methodology, the converter has been implemented in a 130-nm CMOS process using integrated capacitors of total size 2.2 nF. Simulation results show that the optimized converter circuit achieves an efficiency range from 83.41% to 74.69% for a load current of $100~\mu \text{A}$. [ABSTRACT FROM AUTHOR]

In this paper, a generic, low-noise, negative-voltage generator with wide tuning range and moderate driving capacity is presented. The highly integrated solution, incorporating a fully-integrated charge-pump and a regulator block, requires only one off-chip capacitor that can be shared with the supply decoupling capacitors. The fully integrated charge-pump operation is analyzed quantitatively, and a closed-form expression of its output impedance is derived. Powered from a single 3.3-V dc input, the output has a tuning range from −4.4 to +2.1 V for biasing applications, while the design supports a maximum load current of 250, 550, and $800~\mu \text{A}$ for the regulated output voltage at −3.0, −1.5, and 1.5 V, respectively. The measured steady-state ripple is under 3 mVPP, while the noise voltage at the charge-pump operating frequency harmonics is below 130 $\mu \text {V}_{\mathrm{ rms}}$ and the noise floor is under $5~\mu \text {V}_{\mathrm{ rms}}$. The design is also the application verified with a gallium nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180-nm process, the prototype chip occupies an area of 0.55 mm2. [ABSTRACT FROM AUTHOR]

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results. [ABSTRACT FROM AUTHOR]

A wide-input-range (5–115 V) current-accuracy-enhanced dc–dc LED driver is presented in this paper. A feedforward synchronous current control (FSCC) scheme is developed to improve the LED current accuracy over wide ranges of input and output voltages. In the FSCC, a reconfigurable valley current sensor is proposed to provide accurate positive and negative valley inductor current information for the controller corresponding to hard- and soft-switching modes, respectively. A dynamic peak reference generator is developed to automatically adjust the peak current reference value dependent on input and output voltages for reducing the deviations of the average LED current under different input voltages and numbers of output LED, thereby improving the current accuracy. Implemented in a 0.5- $\mu \text{m}$ 120-V CMOS process, the experimental results show that the proposed LED driver IC achieves a current accuracy within ±6.0% of the average LED current of 350 mA over an input voltage range from 5 to 115 V and numbers of series-connected LEDs from 1 to 25 by using only a small inductor of 10 $\mu \text{H}$. Compared with the state-of-the-art synchronous current control scheme, the variations of the LED current can be reduced by 2.3 and 4.2 times in the hard- and soft-switching modes, respectively, with the proposed LED driver using the FSCC. [ABSTRACT FROM AUTHOR]

This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

It is essential to retain improved efficiency in a dc–dc converter over a wide load current range to extend the battery-life in portable devices. This requires a multi-mode controller, consisting of pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) schemes. However, existing approaches attempt to integrate structurally different controllers; thus it is difficult to achieve a seamless controller transition. While a digital platform offers controller configurations, it remains difficult to identify a suitable digital PWM/PFM technique and decide on its sampling mechanism to achieve stable behavior. This paper proposes a unified digital PWM/PFM scheme which shares a common digital PWM (DPWM) block and has the provisions for online controller configuration and automatic (switching) frequency adaptation. The proposed scheme retains improved efficiency over a wide operating range and inherently achieves seamless controller transitions. Further, a unified discrete-time framework is proposed for the analysis and design of the proposed multi-mode controller. Buck and boost converter prototypes are tested and the proposed controller is implemented using a field-programmable-gate-array device. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling of output voltage. By analyzing the snubber circuit and its resonance on the primary side, this paper implements a proposed accuracy knee voltage detection (AKVD) technique to compensate for the induced resonance frequency. Furthermore, the proposed constant current (CC) regulator ensures the accuracy of CC mode by compensating the sensing current error caused by the switching delay of the power transistor. A prototype consisting of a test chip fabricated with a 0.5\mu \text m BCD process demonstrates a voltage accuracy exceeding 99.63%. This is achieved by mitigating abnormal detections and thus ensuring correct control of charging current throughout the charging period. [ABSTRACT FROM AUTHOR]

This paper presents a new method for detecting and reversing the polarity of a low-voltage thermoelectric generator (TEG) in inductor-based converters. The proposed technique makes use of the inductor response to a voltage change due to the flip in the TEG polarity. The inductor voltage provides two distinguishable states which correspond to the normal and the reversed TEG polarity. A switch matrix circuit is then used to correct the polarity by physically reversing the TEG connection. The detection circuit along with the switch matrix provide a positive input voltage from the TEG to the inductor-based converter. The proposed technique is an efficient polarity detection with all-digital implementation, fully integrated, small area and power overhead. The prototype chip is fabricated in 65-nm CMOS and occupies an area of 0.09 mm2. Measurement results confirm a maximum efficiency of 70% at 50 mV TEG voltage and 40~\mu \text A output current. The proposed technique is part of an autonomous thermal energy harvesting system that detects and corrects the TEG polarity. [ABSTRACT FROM AUTHOR]

High step-up conversion is an indispensable feature for the power processing of low voltage renewable sources in grid-connected systems. Motivated by this necessity, this paper presents a study on non-isolated dc-dc converters based on the conventional Boost converter that can provide such feature with high efficiency. By the topological variation and gain cell concepts, it is demonstrated that these converters can be treated as a unique generalized converter, called Boost Converter with Gain Cell (BCGC). The operating principle, the key waveforms and the components stresses of the BGCG are analyzed for the continuous-conduction mode, independently of the employed gain cell. A methodology to create the gain cells is developed from the combination of coupled inductors and voltage multiplier techniques. In order to verify the realized analysis, a 150 W prototype concerning to the proposed generalized converter and able to operate with several different gain cells is developed for the comparison between theoretical and experimental static gain results. [ABSTRACT FROM PUBLISHER]

This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 \mu\textA to 800 \mu\textA. The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 \mu\textA and regulated load voltage of 1 V. [ABSTRACT FROM PUBLISHER]

A pair of universal current mode control schemes for charging a Li-ion battery for mobile applications are discussed in this paper. The peak-current mode control schemes, based on a single control loop, is universal because it is designed with a single-stage buck charger for both a conventional wall adapter dc source as well as a solar photovoltaic (PV) module of comparable specifications. The charging schemes remove the need for an extra MPPT (maximum power point tracking) power converter stage. This control scheme is non-linear and incorporates all possible scenarios: mode of operation of a battery, current charging rate and power characteristic of input source. The algorithm uses need-based MPPT and ensures minimal battery discharge, and also uses minimum number of sense variables in the circuit. The methods differ in the way MPPT is implemented: perturb and observe (P&O) and fractional open circuit voltage. Simulation results demonstrating battery charge profile, validity of the algorithm under varying insolation conditions and platform workloads are presented, along with a discussion of the trade-offs of the two methods. Proof-of-concept hardware results are also provided. [ABSTRACT FROM AUTHOR]

In this paper, the mathematical foundations of the security implications of utilizing various on-chip voltage converters as a countermeasure against differential power analysis (DPA) attacks are investigated. An exhaustive mathematical analysis of a recently proposed converter-reshuffling (CoRe) technique is presented where measurement to disclose (MTD) is used to compare the security of the proposed on-chip CoRe regulator with the security of conventional on-chip voltage regulators. A DPA-resistant and lightweight advanced encryption standard (AES) engine implementation that leverages the CoRe technique is proposed. The impact of the centralized and distributed placement of the voltage regulators on the security of a pipelined AES engine is explored. The security implications of the relationship between the clock frequency of the device under attack and the switching frequency of the voltage regulator are investigated. As compared to an unprotected AES engine, the MTD value of the proposed improved pipelined AES engine with a centralized on-chip CoRe regulator is enhanced over 9100 times. [ABSTRACT FROM PUBLISHER]

A maximum-power-point-tracking DC-DC boost converter to harvest energy from sub-\muW power sources is presented. For available input-power levels below 1 \muW, voltage boosting is achieved by operating all circuits in the sub-threshold region, and by switching the DC-DC converter at tens of Hz, thereby reducing switching losses. The paper further explores the possibility of energizing the DC-DC inductor for an optimum duration, such that switching and resistive losses are minimized. The sub-\muW energy harvesting circuit uses an area of 0.2 mm^2 on a standard 180 nm CMOS process, and utilizes an auxiliary voltage source for start-up. The designed and fabricated system is more than 50% efficient when the available power is greater than 2 \muW. The circuit can harvest energy whenever the available power is more than 0.3 \muW. Efficiency at 0.3 \muW is 25%, at 0.5 \muW is 37% and at 1 \muW is 48%. The complete IC consumes 50 nA for internal operations and the input voltage can be as low as 70 mV. [ABSTRACT FROM PUBLISHER]

This paper proposes a fast transient quasi-V^2 fixed-frequency hysteretic buck converter designed and fabricated using TSMC 2P4M 0.35-\mum CMOS process. The proposed converter can achieve fixed frequency switching through a novel phase-locked-loop-based two-stage adaptive window control. Under ultralight load conditions, the proposed converter operates in a pulse frequency modulation mode to reduce the switching loss and improve light load efficiency. A quasi-V^2 technique is applied for obtaining inductor current information without relying on an output capacitor with a high equivalent series resistance; therefore, the output voltage ripple can be reduced. The experimental results show that the proposed converter can operate at a load current ranging from 18 to 700 mA, a supply voltage ranging from 2.7 to 4.2 V, and an output voltage of 1.2 V. The off-chip inductor and output capacitor are 2.2 \muH and 10 \muF, respectively. Through the PLL control, the switching frequency is maintained at 1 MHz. The transient response time is approximately 5 \mus, and the highest efficiency registered is 95.6%. [ABSTRACT FROM AUTHOR]

Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, methods of consecutive read with long refresh intervals and fast write for the proposed design are also discussed. Another highlight of this work is the analysis of the proposed memristor-based crossbar architecture which has a series of excellent features, such as good-compatibility, high-density, non-volatility, low-power, and good-scalability. Simulation results also show that the proposed memory array has superior performances compared to other memristor-based arrays proposed in the existing technical literature. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 \mum show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3\times, 19\times, 29\times respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations. [ABSTRACT FROM AUTHOR]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

Power management of mobile digital systems-on-chip necessitates large voltage regulation performances. DC/DC converters used to supply digital cores are facing stringent constraints with respect to load transients, reference tracking and accuracy. The fast transient response offered by sliding-mode control is well suited to DC/DC converters with fast varying load. Fixed switching-frequency is also mandatory for EMI and noise related issues. Fixed-switching frequency sliding-mode control has been experimented as a multi-loop system. There is a necessity to investigate the stability when multi-loops interact and the parameter set for each loop is quite large. The paper details a methodology for the stability analysis of a frequency-controlled sliding-mode DC/DC converter. The proposed stability analysis takes the possible cross-interactions into account and can be used to optimise the DC/DC controller without the limitations of a non-interaction criterion. As a verification a DC/DC converter is implemented in CMOS 130 nm. Experimental results agree with the analysis main recommendations. [ABSTRACT FROM AUTHOR]

A 6.78 MHz single-stage transmitter (TX) using a reconfigurable regulating class-D power amplifier (PA) for wireless power transfer (WPT) applications is presented. Based on a 3-mode modulation scheme, the TX achieves power regulation and transmission with only one power stage. A discontinuous-conduction-mode (DCM) zero-voltage switching (ZVS) scheme is adopted to reduce switching loss. A control loop is set to regulate the output voltage of the WPT receiver (RX) by automatically adjusting the transmitting power. With dual-loop control and a proportional-integral (PI) compensation scheme, the loop achieves tight regulation and fast response. The controller is implemented digitally to benefit from the AirFuel® embedded Bluetooth communication link. The PA was fabricated with a high-voltage 0.35 μm CMOS process, and the digital controller with a standard 0.35 μm CMOS process, respectively. Measurement results show that the output voltage of the RX was correctly regulated to 11.7 V under a load change of 50mA to 500mA, and the WPT system could deliver a maximum power of 7.3 W to the RX over a distance of 4.0 cm, and achieved TX to RX peak efficiency of 57.3%. [ABSTRACT FROM AUTHOR]

Dedicated to neuron stimulation circuits, a stage-selective negative voltage generator is proposed to enhance the overall power efficiency. Since the supplied voltage of the stimulus driver is subject to applications and treatments, an extensive output requirement of supply is demanded to achieve energy-efficient stimulation. The charge pump is implemented as a negative voltage generator for on-chip design. In a limited area, excess power loss is eliminated by reconfiguring the cascaded architecture and clocks. Digitally programmable voltage levels can be outputted by varying the number of stages dynamically. The function of stage selection is achieved by the proposed stage-selective scheme. With appreciate control, the stage-selective negative voltage generator can maintain higher power efficiency under different output voltage levels and loading conditions. The technique improves 40% power conversion ratio at most but only leads to an increment of 8% in area occupation. The measured output voltage covers from −0.3 V to −9.3 V within a maximum 5.5-mA output current, which is verified in a 0.25- $\mu \text{m}$ BCD process. [ABSTRACT FROM AUTHOR]

A two-stage hybrid power management unit (PMU) is presented with a highly-efficient novel ON-OFF LDO as the second stage and uses a switched-capacitor dc-dc divider as the first stage. The design targets IoT applications that operate across a wide range of load from sub-microwatt to 100’s of microwatts. The first stage provides a step-down using selectable sizing of its switches to improve efficiency to >95% across the target range of load current. The output voltage that is divided from the first stage is then regulated using the proposed ON-OFF LDO with a dropout voltage of < 30mV. The hybrid architecture regulates a 1.3V input to 0.4V and achieves a power efficiency of >80% for load ranges 1μ - 240μA. The design is fabricated in 28-nm CMOS technology. [ABSTRACT FROM AUTHOR]

An active electronic interface for maximizing the power extracted from a resonant piezoelectric vibration harvester by means of a multi-variable Maximum Power Point Tracking (MPPT) technique is presented. The input voltage of the electronic interface is dynamically adapted in order to ensure that the maximum power is extracted even if the vibration characteristics change with time. The digital control unit updates the amplitude, the phase and the frequency of such an input voltage without requiring the high-frequency sampling and elaboration of the harvester current or voltage. The unit exploits only the information on the vibration frequency kept from a small piezo accelerometer and a low-frequency sampling of the DC current. The implemented algorithm is as simple as the widespread Perturb & Observe algorithm, but it allows the extraction of significantly more power from the harvester. The power increase for a piezoelectric harvester with the proposed electronic interface is investigated both theoretically and experimentally. By using a commercially available piezoelectric harvester, the maximum power tracking performance of the proposed active interface is experimentally compared with that of a usual AC/DC converter with Perturb & Observe MPPT control. [ABSTRACT FROM AUTHOR]

The proposed SFE IC adopts an eight-channel H-bridge structure with an integrated voltage compliance monitoring circuit. It has stimulation current ranged from 0.78mA to 6.2mA selected by 3b control and the stimulation current level can be controlled with 7b resolution within a selected current range. The current range can be expanded by using a high current option ranged from 2.71mA to 21.7mA under 3b control. The worst DNL and INL of the stimulation current source are 0.32 LSB and 0.3 LSB, respectively, from all the current ranges. The average mismatch between the cathodic and anodic current pulses in a biphasic stimulus is measured as 0.034% without using charge balancing techniques. The voltage compliance monitoring circuit is based on triode detection of a sensing MOSFET and it shows the detection accuracy of 45mV from its measurement results. The maximum steady-state voltage across the electrodes/ solution interface (resting potential) is also rigorously analyzed and verified through bench-top and saline experiments by utilizing the proposed stimulator. The SFE IC was fabricated in $0.18~\mu \text{m}$ 24 V CMOS process. [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

A low energy-noise switched-capacitor (SC) sensor interface for resistive bridge sensor is presented. The SC amplifier achieves low-power metric with two operating modes using operation-phase-dependent biasing and compensation scheme in the op-amp design. This novel op-amp works in high-bandwidth high-power mode to sample the bridge signal for 13\mu \text s twice and in low-bandwidth low-power mode for 474\mu \text s over 500\mu \text s measurement interval. To further reduce the power of the SC amplifier in system level, a SC level-shift design is adopted. Regarding offset calibration, a capacitor divider based trimming scheme is implemented to generate the mid-point DC output voltage under the constraint of the feedback capacitor size. Implemented in 65 nm CMOS, the SC interface together with the regulator, voltage reference and trimming circuit occupies an area of 0.358 mm2. For the first test setup utilizing Half Wheatstone Bridge, the proposed SC amplifier consumes 12.3\mu \text W at 1 V regulated supply with a 2 kHz system clock. The measured Signal-to-Noise Ratio (SNR) of SC circuit is 55.6 dB. In the second test setup using a commercial sensor with 0.092 mV/kPa sensitivity, the interface has demonstrated the sensing function with sensitivity of 3.52 mV/kPa. Finally, compared to the representative prior-arts, this work has achieved the best energy-noise figure-of-merit at identical fractional resistance change. [ABSTRACT FROM AUTHOR]

A current-based resonant power delivery (CRPD) technique with multi-cycle switching has been presented that enables efficient inductive power transmission at large distances. Unlike the conventional inductive link, in which the receiver (Rx) LC-tank is utilized as a voltage source, the proposed CRPD switches the Rx LC-tank for several cycles in a novel fashion to utilize it as a current source. Therefore, the voltage across the load (RL) can be significantly higher than the Rx LC-tank voltage. This eliminates the need for DC-DC charge pumps or AC-DC voltage multipliers, which require several capacitors and diodes. In CRPD, the energy is first stored in the Rx coil by shorting the Rx LC-tank for several power carrier cycles. At the peak of Rx coil current, the coil energy is then transferred to RL for a quarter of the power carrier cycle. The circuit theory behind CRPD has been developed and verified with simulation results. A proof-of-concept CRPD was also characterized in measurements to demonstrate its feasibility. In measurements, CRPD was capable of achieving the DC voltage of 3.1 V across an RL of 100 \textk\Omega, by switching the Rx LC-tank at 50 kHz with an AC voltage amplitude of 1 V across the Rx coil at the operation frequency of 1 MHz. Moreover, compared to a conventional inductive link followed by a passive rectifier, to achieve a minimum DC voltage of 2.8 V across an RL of 100 \textk\Omega the proposed CRPD extended the range from 7 cm to 13 cm for the same voltage across the transmitter coil. [ABSTRACT FROM AUTHOR]

A floating buck controlled multi-mode dimmable light-emitting diode (LED) driver that uses a stacked NMOS switch is presented, which reduces static operational current and eliminates auxiliary winding to simplify design and cost. The accuracy of the output current benefits from the use of a line-voltage compensation technique which can mitigate the effect of line-voltage fluctuation on current consistency. The proposed LED driver is implemented in 0.5 \mum 5V/40 V backend 2P2M CMOS process and occupies a die size (with pads) of 1.17\times 0.84\ mm^2. The experimental results show that the proposed LED driver achieves peak power efficiency of 95.4% across a wide range of input voltage from 85 to 264 Vac and a wide range of series-connected load LEDs from 11 to 27. The worst-case line regulation and load regulation of the output current are 0.28% and 0.25%, respectively. Measurements further show that the startup time is only 34.8 ms at 220 Vac with 50 Hz-input and multi-mode dimming can be easily implemented. [ABSTRACT FROM AUTHOR]

A high efficiency, maximum power point tracking (MPPT) power management unit (PMU), with 3.6 \mmb\mu\bf W quiescent power, aimed at a thermoelectric generator (TEG) array is presented. The proposed energy harvesting PMU is made up of a boost converter with a cascaded capacitor-less low drop-out (CL-LDO) voltage regulator. The segmented approach allows the PMU to match the TEG array's changing dynamic series resistance via the boost converter and simultaneously provide voltage regulation with adaptive, high switching noise rejection via the CL-LDO. The boost converter's switching frequency (f{sw}) is tracked via a Sense-and-Control loop which modifies the CL-LDO's power supply rejection (PSR) characteristics to place a notch in the PSR transfer function around the average f{sw}. Experimental results show an overall system efficiency better than 57% @ 1.6 V output voltage, PSR of 40 dB at f{sw}, and a notch-tuning range of 15–65 kHz. The total active area is 0.93 mm^2 in 0.5 \mum CMOS. [ABSTRACT FROM PUBLISHER]

We present a highly efficient RF transmitter over broad average power range using a multilevel envelope-tracking power amplifier (ML-ET PA). The ML-ET PA delivers enhanced efficiency at a back-off power region for handset applications. The supply modulator consists of a linear regulator and a switching converter. The DC supply of the linear regulator is adjusted according to the average power of the envelope signal, and the power-supply-independent class-AB output stage is employed to avoid the crossover distortion generated by the different DC supply voltages. The switch current level is not optimally adjusted by itself following the power back-off level, because the DC supply voltages of the linear regulator and switching converter are different. For the optimum operation over the entire power region, the switch current level is adjusted by detecting the input envelope voltage level. For a 20-MHz long term evolution signal with a 7.5 dB peak-to-average power ratio, the proposed supply modulator delivers a peak voltage of 4.5 V to a 6.5 \Omega load with a measured efficiency of 75.9%. The proposed ET PA delivers a power-added efficiency (PAE) of 40%, gain of 28.8 dB, evolved universal terrestrial radio access adjacent channel leakage ratio of -35.3 dBc, and error vector magnitude of 3.23% at an average output power of 27 dBm and an operating frequency of 1.71-GHz. At a 10 dB back-off point, the PAE is improved from 14.5% to 18.7% compared to the conventional ET PA. [ABSTRACT FROM AUTHOR]

Traditional slope compensation (SC) method is an effective way to control fast-scale instabilities present in peak current mode (PCM) controlled boost PFC converters. However, with the SC method, envelope of inductor current deviates from a desired sinusoid especially near the zero crossings, which causes the system power factor to reduce to values lower than what is possible without compensation. To tackle this problem we propose a hybrid dynamic compensation (HDC) scheme, which incorporates a combination of zero-perturbation dynamic compensation (ZPDC) and ripple compensation. The proposed HDC scheme can suppress the fast-scale instabilities and also ensure average inductor current tracks a desired sinusoidal reference which is not possible with the ZPDC scheme alone where only the peak inductor current can track a desired sinusoidal signal. Furthermore, with the proposed HDC scheme the total harmonic distortion (THD) and power factor (PF) are improved in comparison to the SC and ZPDC schemes as well as to the case without compensation. Moreover, operating range of a control parameter is determined analytically subject to some assumptions. Extensive simulation and experimental results are provided to validate the theoretical analysis and the feasibility of the proposed HDC scheme. [ABSTRACT FROM AUTHOR]

The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area. [ABSTRACT FROM AUTHOR]