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This paper proposes an LCCC and CCL compensated wireless servo motor control circuitry utilizing the merits of fundamental and third harmonic. With this circuitry, the motor side needs no additional power supply and controller, which significantly reduces the difficulty of maintenance. Besides, benefiting from the proposing of CCL compensating topology and utilizing of the self-driven circuitry, the secondary operates in fully resonant state and the motor direction control H-bridge is self-driven by the LC frequency selecting circuitry (FSC). Moreover, compared with the conventional motor control circuitry, because of the use of fundamental and third harmonic, the power equalization becomes significantly easier, and zero voltage switch (ZVS) can be realized at the same time; Besides, motion direction control of the motor is simpler with only a single pole double throw (SPDT) at the transmitter side. In addition, system resource consumption is reduced compared with conventional motor drive topologies. In this paper, an 180W prototype is built for experimental verification, and the result shows a good power equalization capability and a transfer efficiency reaching up to 90% at the distance of 10cm. [ABSTRACT FROM AUTHOR]

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm2. When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper describes a hybrid binary frequency-phase shift keying (BF-PSK) receiver architecture designed with a technique involving both the received signal frequency and phase for low-power operation with relatively high data rate. The method enables the demodulation of the incoming signal without synchronization requirements, which reduces the design complexity and power consumption. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. A novel low-noise amplifier architecture is introduced in this paper as well. The Medical Implant Communication System (MICS) band receiver was designed and fabricated in a standard 65nm CMOS technology, and the measurement results demonstrate the feasibility of this architecture. As a proof-of-concept, it operates with a 416 MHz carrier frequency at a state-of-the-art data rate for sub-milliwatt receivers of 10 Mbps, while consuming $610~\mu \text{W}$ from a 1 V supply. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of a passive front-end (PFE) for low-power receivers. The freedom of the antenna impedance is observed and exploited to propose an inductive-antenna-based PFE. Analytical methods for the desired signal transfer and noise behavior of the proposed PFE are presented to offer insight into the proposed technique and facilitate the design. The analysis suggests that the inductive-antenna-based PFE offers higher voltage gain and lower noise figure than a standard $50~\Omega $ -based PFE does, which is confirmed by simulations. The proposed PFE and a baseband bandpass amplifier are designed in 0.18- \mu \text{m} CMOS technology for the 402–405 MHz band of the IEEE 802.15.6 WBAN standard. Their combination exhibits a passive voltage gain of 11.6 dB, a NF of 14.7 dB, and an in-band IIP3 of 3.6 dBm, while dissipating 1.1 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier’s output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ± 0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications. [ABSTRACT FROM AUTHOR]

This paper presents an analog front-end (AFE) circuit with marked timing point for pulsed time-of-flight LiDAR that employs either sampling- or event-based timing approach. The proposed AFE adopts a dual-mode structure for its pre-amplifier which can be configured as a charge-sensitive amplifier (CSA) or a gated active load-assisted TIA (GALA-TIA), depending on the intensity of input current. As a result, both the sensitivity and dynamic range (DR) of the AFE have been effectively improved. In addition, the zero-crossing point of the output signal has been marked as the timing point with a built-in pulse shaper, which allows the back-end circuits of LiDAR receiver discriminate the timing conveniently and accurately. The measured input-referred RMS noise current of the proposed AFE is 37 nA. With dual-mode control, a linear output DR of 80 dB and a wide timing DR of 96 dB with walk error no more than ±160 ps have been achieved. For single-shot measurement application, only CSA mode was enabled and the pulse widths of saturated output signals have been measured to compensate the walk errors, which realized a timing DR of 78 dB with accuracy of ±150 ps. The averaged power consumption is 66 mW and the total silicon area is $0.79\times 0.42\,\,mm^{2}$ in 0.18- $\mu \text{m}$ CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a compact single-ended inverter-based transceiver with swing improvement for short-reach links. The low output impedance of the transmitter enlarges the output swing and the eye size to overcome large single-ended noise while relaxed impedance matching provides good signal integrity. For good area efficiency, the proposed transmitter utilizes an inverter driver which is much smaller than the conventional source-series termination driver and thus occupies only $42.5 ~\mu \text{m}^{2}$. By taking the advantage of a large signal swing, the receiver consists of only four slicers and latches to minimize area overhead and to simplify the design. The transceiver was fabricated in 28-nm CMOS technology and tested at supply voltage of 1.13 V. The transmitter achieved a large output swing of 850 mV, which is 50.4 % larger than the conventional source-series termination transmitter. At the far-end of a channel consisting of a 1 m SMA cable and a 17 mm printed circuit board trace, the transmitter achieved eye openings of 440 mV and 234 mV at 16 Gb/s (−2.7 dB) and 20 Gb/s (−8 dB), respectively. Even with a large switching noise of 100 mV, the in-situ eye at the receiver was measured 114 mV with 7.4 dB loss. [ABSTRACT FROM AUTHOR]

Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric h_{t} are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 \mu\textW). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 10^9 and 10^10, as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd. [ABSTRACT FROM AUTHOR]

Private Set Intersection Cardinality (PSI-CA) is one of the most concerned issues with the protection of privacy, in which two parties jointly compute the intersection cardinality without revealing their respective private sets. There are important applications of PSI-CA in real society, e.g., strongly privacy-preserving data statistics in contact tracing for health authorities to fight the outbreaks of highly contagious diseases. In this paper, we present a novel quantum PSI-CA protocol, in which we adopt oblivious quantum key distribution, secure quantum summation and quantum counting algorithm. The proposed PSI-CA protocol not only ensures the approximatively perfect security but also achieves the linear communication complexity, i.e., ${O(N)}$. Furthermore, we define a new privacy protection problem, i.e., Privacy-preserving Condition Query (PCQ), and provide an efficient solution to the PCQ problem based on the proposed quantum PSI-CA protocol. Finally, we verify the correctness and the feasibility of the proposed quantum PSI-CA protocol by circuit simulations in IBM Qiskit. [ABSTRACT FROM AUTHOR]

There are practical applications requiring the wireless power transfer (WPT) system to supply multiple output voltages to a variety of loads. In this paper, in order to achieve this goal, multiple double T resonant circuits are connected to the common port of the receiver side. Based on the modeling and analysis of the double T resonant circuit, it is found that the load-independent output and input zero phase angle (ZPA) can be derived. The proposed WPT system presents the following merits: 1) output voltages are load independent and can be controlled synchronously against the disturbance from input DC source and mutual coupling by using only one closed loop; 2) the output voltages can be adjusted individually to different levels by configuring circuit parameters; 3) only passive components are used to achieve multiple outputs. The power loss can be reduced due to the parasitic resistance of the passive component is very small and can be negligible; and 4) the reactive power losses are minimized due to the input ZPA of the system. An experimental prototype with two output channels is built, based on which the load independent and the controllable characteristics of the output voltages are verified. [ABSTRACT FROM AUTHOR]

This paper presents a compact impulse-radio ultra-wide band non-coherent receiver architecture for high data rate wireless neural recordings from active high-density CMOS-probes. The system is capable of receiving, synchronizing, and demodulating a continuous on–off keying pulse stream at 1 Gb/s and 4 GHz center frequency using an active area of 0.34 mm2 and a single 31.25 MHz crystal reference. An asynchronous threshold energy detector, including a pulse enhancement baseband with an all-digital back-end, recovers incoming transmitter clock (CDR) and acquires packet synchronization based on a data-aided mechanism (DPR). Results shows that a prototype of the receiver integrated in a 130 nm CMOS process recovers synchronization in 30 ns. The system includes I/O output buffers and driver logic at 1.8 V supply operating at 1 GHz on a 50 $\Omega $ load and crystal oscillator. Overall, it consumes 115 pJ/pulse, while the receiver core only consumes 12 pJ/pulse. This paper presents the receiver architecture, and experimental results show a sensitivity of −38 dBm at 10−3 packet error ratio. [ABSTRACT FROM AUTHOR]

In this paper, the first dual-band sub-sampling receiver front end with sampling frequency optimization to meet the ultimate receiver error vector magnitude (EVM) of −40 dB over wide input power range of 19 dB is proposed. A systematic sub-sampling receiver chain EVM optimization with respect to major system-level impairments, such as noise folding, sampling frequency, IQ mismatches, phase noise of the sub-sampling clock, and unit capacitor value realizable at the decimation filter, is presented. The proposed dual-band sub-sampling receiver has a 26–41 dB continuously tunable gain for 2.4 GHz and 26–38.5 dB for the 5 GHz WLAN band. Continuously tunable gain ensures the ultimate receiver EVM performance over wider input power levels. In addition, the 5 GHz band is continuously tunable from 4.5 to 5.7 GHz. An active balun feedback low-noise amplifier followed by a sub-sampling down-conversion mixer is implemented to down-convert both WLAN bands to an intermediate frequency in the range from 445 to 538 MHz. Sub-sampling frequency optimization proposed in this paper down-converts both WLAN bands with the sampling frequency from 1.78 to 2.15 GHz to reach the target EVM. Additionally, a switched capacitor decimation filter running at 90 MHz is implemented to provide dual functionalities of down-conversion to baseband and band selection. A test-chip is implemented in a 1.2 V 65-nm CMOS technology. The proposed dual-band sub-sampling receiver occupies a total active area of 0.72 mm2 and has a total power dissipation of 55.6 mW. The overall receiver chain shows a noise figure of 11.5 dB at the highest gain and an IIP3 of −8 dBm at the lowest gain. [ABSTRACT FROM AUTHOR]

This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ($\Delta \Sigma$) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $\Delta \Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $\Delta \Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $\Delta \Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm2. The $\Delta \Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $\Delta \Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz. [ABSTRACT FROM AUTHOR]

Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7–7.5dB and a Tx insertion loss of 3.9–5.6dB. Self-interference cancellation of >50dB is measured for 20-MHz RF bandwidth in 2.4–2.6-GHz frequency range. [ABSTRACT FROM AUTHOR]

This paper proposes a self-powered disposable supply-sensing biosensor platform for big-data-based healthcare applications. The proposed supply-sensing biosensor platform is based on bio fuel cells and a 0.23-V 0.25- $\mu \text{m}$ zero- $V_{\text {th}}$ all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-driven architecture uses zero- $V_{\text {th}}$ transistors, which enables low voltage operation and a small footprint, even in a cost-competitive legacy CMOS. This enables converterless self-powered operation using a bio fuel cell, which is ideal for disposable healthcare applications. To verify the effectiveness of the proposed platform, a test chip was fabricated using 0.25- $\mu \text{m}$ CMOS technology. The experimental results successfully demonstrate operation with a 0.23-V supply, which is the lowest supply voltage reported for proximity transmitters. A self-powered biosensing operation using organic bio fuel cells was also successfully demonstrated. In addition, an asynchronous inductive-coupling receiver and an off-chip inductor for performance improvement were successfully demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents a single-chip impulse-radio (IR) radar transceiver that utilizes a novel continuous sweep-clock generator. While requiring low power and small area, the proposed clock generator enables a versatile IR radar operation with millimeter resolution. The radar detection range and update rate are adjustable by an on-chip delay command circuit or by an external master. The IR radar transceiver, working with transmission and reception clocks, incorporates a spectrum adjustable transmitter and a wide-band sampling receiver. The recovered echo pulses from the radar are distinguishable in an expanded time scale. For the first time, generalized analyses on the radar range for time-expansion IR radars are established. The single chip radar transceiver is fabricated in a 130-nm CMOS technology occupying a chip area of 1.0 mm2. The measurements show that the echo pulses are recovered with a millimeter range resolution, while dissipating 30 mW. Respiration motions are successfully captured with the prototype radar. [ABSTRACT FROM AUTHOR]

The Direct RF-to-Digital $\Delta\Sigma$ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requirements and also improves the noise transfer function of the loop filter. However, the RF feedback poses several challenges, especially making the design methodology more complex. In contrast to classical receiver architectures, the blocks of the Direct RF-to-Digital $\Delta\Sigma$ receiver cannot be designed, analyzed, and simulated independently. Besides, conventional design methodologies for $\Delta\Sigma$ Modulators cannot be applied for this kind of receiver due to the presence of the RF blocks and the RF feedback inside the loop. This paper presents a new design methodology suited for this family of receivers. The proposed methodology covers simulation approaches, system design, and non-ideality impacts on the receiver. A design example of a multi-band multi-standard receiver for GSM/WCDMA/LTE is considered throughout the paper to demonstrate this design methodology. [ABSTRACT FROM PUBLISHER]

In a capacitive wireless power transfer system, due to the pF-level coupling capacitance, resonant inductors are commonly used at the primary side to boost voltage and at secondary side to boost the current. However, the inductors are bulky, in particular when it comes to integration, thereby not preferred by some space-sensitive applications like smartphones, smart glasses and headphones. This paper proposes a capacitive wireless power transfer architecture with no inductors at the receiver side. A high conversion ratio step down switched capacitor converter (SCC-CPT), rather than inductors, is used to compensate for the impedance mismatch between the secondary side of the capacitive coupler and the load. The analysis method and its associated design procedure of the SCC-CPT system is developed with the target of clarifying the tradeoffs among the secondary side efficiency, coupler voltage stress, receiver side integrability, and the primary side compensation network gain. Finally, a 7.5 W, 12 MHz SCC-CPT prototype was constructed to validate the proposed analysis and design. The measured system efficiency is 75.6 % at 7.5 W output, and the secondary side switched capacitor converter efficiency is 96.4 %. [ABSTRACT FROM AUTHOR]

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate $< 1\text{E}$ -10 with a power efficiency of 4.75 pJ/bit. [ABSTRACT FROM AUTHOR]

The paper describes the FPGA implementation of a novel position evaluation algorithm based on the time difference of arrival (TDOA) principle that combines the characteristics of an Orthogonal Frequency Division Modulation (OFDM) symbol with the properties of the Zadoff-Chu mathematical sequences. The resulting system is highly scalable and its characteristics are easily adaptable to different operating scenarios. The algorithm has been implemented using the Stratix IV-E EP4SGX70HF35C3 FPGA, requiring about 112k bit of memory and less than 44k logic elements of which about 16k are registers. The paper describes the algorithm and its FPGA implementation along with experimental results validating the system performance even in the presence of multipath interferences and showing precision in target position estimation that is better than 2 cm. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode, dynamically zooming analog to digital converter (ADC). The architecture is based on a 5b interpolating flash ADC as the zooming unit and a passive discrete-time $\Delta \Sigma $ modulator as the fine conversion unit. The proposed ADC provides a dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in $0.13~\mu \text{m}$ CMOS technology and it achieves an SNDR of 83/75.7/73.2/67 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/4.7/8.1/10.3mW power consumption from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper discusses a wideband variable-gain amplifier (VGA) implemented in a 28-nm FDSOI CMOS technology. This VGA employs optimal-biasing and differential large-signal pre-distortion linearizations that operate over all gain settings and over its frequency range. The 0.4-to-4-GHz VGA, which consists of its core circuit and an output buffer, exhibits a wideband gain ranging from 4.6 to 12 dB in 1-dB steps and an input return loss higher than 10 dB while demonstrating a worst-case IM3 of −54 dBm across the gain range at ~0-dBm output power and noise figures from 3 to 5.9 dB at 12 dB gain. The VGA and buffer consume 15 mA and 60 mA from a 1.5 V supply, respectively. The total chip area, including the bond pads, is ${1\times 1\,\text {mm}^{2}}$. [ABSTRACT FROM AUTHOR]

Multiple output wireless power transfer (WPT) system has a great potential to be used in applications where multiple receivers need to be powered simultaneously, including wireless office table, logistic sorting robots, and magnetic resonant imaging (MRI) equipment. For the sake of reducing no-load losses and avoiding leakage magnetic fields, it is desirable to only switch on those transmitter coils that are covered by receivers and switch off the rests. To realize this, however, bidirectional power switches, sensors and control logic are needed, which are expensive, bloated, and lossy. This paper proposed a novel receiver-controlled coupler (RC-Coupler) that can realize switching on/off of transmitter coils without using bidirectional switches, sensors, and control. The structure, design considerations, and leakage fields of the proposed RC-coupler are researched, and its feasibility has been confirmed with a GaN-based 120 W, 6.78 MHz prototype. A power density of 2.78 W/cm3 is reached benefiting from the receiver-controlled characteristics. [ABSTRACT FROM AUTHOR]

Being one non-orthogonal multiple access (NOMA) scheme, interleave-division multiple access (IDMA) can increase the capacity of wireless communication, and therefore, has drawn a lot of attention. Combined with orthogonal frequency division multiplexing (OFDM), OFDM-IDMA system demonstrates good performance with low complexity. In this paper, polar codes are applied to OFDM-IDMA for further performance improvement due to its capacity-achieving capability. The corresponding joint detection and decoding (JDD) scheme is proposed as well. A sign-aided JDD (SA-JDD) scheme is introduced for better efficiency. According to numerical results, the proposed JDD scheme has 1.2 dB performance gain over the separated detection and decoding (SDD) scheme when FER is 10−2. Compared to JDD, SA-JDD scheme reduces the computational complexity by 50% without performance degradation when SNR is 6 dB. In addition, approximation strategy and folding technique are applied for hardware-friendly implementation. The ASIC implementation has demonstrated the advantages of SA-JDD. [ABSTRACT FROM AUTHOR]

This paper presents a feedback receiver for the digital predistortion (DPD) of radio frequency (RF) power amplifiers (PAs). In contrast to conventional architectures, the receiver samples in the frequency domain. By randomly selecting a frequency bin in each sampling interval, the PA model is identified with substantially lower acquisition bandwidth and sampling rate. The receiver prototype is implemented in a 28-nm FD-SOI technology and samples at 4MS/s instead of the full Nyquist rate of 168MS/s for a 20-MHz Long Term Evolution (LTE) signal with spectral regrowth. The prototype is shown to linearize a 4-W small base station power amplifier from an adjacent channel leakage ratio (ACLR) of −35 dBc to −47.7 dBc, after processing only about 250 samples. [ABSTRACT FROM AUTHOR]

A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra transistors. Additionally, a modified charge-sharing bandpass filter with cross-connected transconductors to boost Q-factor is proposed and discussed. The highest voltage gain achieved by the receiver (RX) is 30 dB. The RX noise figure is 3.3 dB at the maximum gain, while the IIP3 is −2.5 dBm at 1 GHz. The area of the receiver is very competitive for the wide band considered, merely 0.137 mm2. The RX and clock generation circuitry drain 25 mA from a 0.9-V supply. [ABSTRACT FROM AUTHOR]

This paper introduces an integrated receiver circuit based on a full-wave adaptive rectifier (AR). It achieves complex impedance matching and enables complexity and cost reduction in resonant wireless power transfer (WPT) systems. The conversion and system efficiency based on this AR receiver are theoretically compared with other receiver architectures by using a WPT system model including all conduction and switching losses. Fabricated in a 0.18- $\mu \text{m}$ BCD process, the AR receiver chip operates at 6.78 MHz, occupies 3-mm2 active die area and includes control and supporting circuitry for independent control of the reactive and resistive parts of the load impedance. The chip was tested in a 2.5-W WPT system, purposely built with extremely low coupling coefficient to enable spatial freedom. Experimental data show that the proposed AR chip achieves up to 96% efficiency. In addition, when used in a WPT system, it delivers 2.15 W with 50.3% system efficiency and 1.96 W with 29% system efficiency for coupling coefficients $k=0.085$ and $k=0.03$ , respectively. [ABSTRACT FROM AUTHOR]

This paper describes a four-element multiple-input multiple-output (MIMO) transmitter (TX) system that features an analog spatial de-interleaver to simplify the baseband-input complexity and increase the spatial matching of the sub-TXs. The MIMO diversity gain and power-combining gain are jointly exploited to relax the output power of the four power amplifiers and eliminate their output matching networks, leading to a compact implementation of the entire TX system. The MIMO effectiveness is improved by introducing an radio-frequency to baseband dc feedback technique that enhances the matching among the sub-TXs against process variation. In the verification, the TX system is co-designed with a compact antenna array-on-PCB that generates a null zone in the propagation pattern, and the electric-field polarization angle, to achieve diversity propagation. All techniques together improve the signal-to-noise ratio or data rate by generating multiple data streams according to the signal power arriving at the receiver over different fading channels. The four-element TX chip fabricated in 65-nm CMOS occupies a die area of 1.44 mm2. It covers an RF range of 0.7–2.5 GHz, and shows an equivalent isotropically radiated power of 23.9 dBm. When transmitting a 20-MHz 64-QAM orthogonal frequency division multiplexing signal at 2.3 GHz, the average system efficiency is 61% and error-vector magnitude is −26 dB. [ABSTRACT FROM PUBLISHER]

System-on-chip (SoC) miniaturization of radiometric sensors could dramatically improve quantitatively the study of Earth’s atmosphere in the microwave- and millimeter-wave frequency regions, enabling cost and weight reductions both for ground- and space-based observation instruments. This paper reports the analysis, design, implementation, and experimental characterization of the first K-band SoC Dicke radiometric receiver implemented in a commercial silicon–germanium technology under Space evaluations. The radiometric receiver exhibits a responsivity of about 760 kV/W and a noise equivalent power of about 232 fW/ $\surd $ Hz at the center frequency of 25.75 GHz. For a bandwidth of 2.5 GHz, the system achieves a resolution of 9 K for a relatively short integration time (1 s), 2.8 K for a medium integration time (10 s), and 0.9 K for a relatively long integration time (100 s). [ABSTRACT FROM AUTHOR]

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB $_\Omega $ and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/ ${\sqrt {Hz}}$. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only $400~\mu \text{A}$ from a 1.2-V power supply. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

Harmonic-reject mixers (HRM) are commonly used in wideband receivers to suppress the effects of spurious harmonic interferers. Both analog and digital HRMs have been proposed in the literature. In existing works, the local oscillator (LO) phases are assumed to be equally spaced. When viewed as a multiuser access system, the drawback of equally-spaced LO phases is that the signature vectors of the desired signal and some harmonic interferers become aligned, limiting the number of interferers that can be attenuated. In this paper, a digital HRM with non-uniform phase spacing that can suppress additional harmonics while being robust to gain and phase mismatches is described. This paper also presents a low-complexity, adaptive and robust digital HRM receiver that enables the fewest LOs and analog-to-digital converters necessary depending on the interference environment for low power. The performance of the adaptive non-uniformly spaced HRM is shown to be significantly superior to existing HRMs with equal LO phase spacing. [ABSTRACT FROM AUTHOR]

A new 10/24-GHz monopulse receiver is developed in this paper. The receiver consists of dual-band or broadband circuits such as low-noise amplifiers, a rat-race coupler, a switch, and mixers. These circuits are fabricated by a standard 0.18-\mum CMOS or an integrated passive device (IPD) technology, and are integrated together in a flip-chip form. The overall chip area is 3.8 mm \times 3.6 mm. With power consumption of 90.6 mW, the receiver results in 16.5/6.9-dB gain, 9.2/14.6-dB noise figure, -22.3/-23.7-dBminput P1\ dB, and 23.6/21.5-dB sum/difference amplitude ratio in the 10/24-GHz bands. Moreover, the monopulse measurement also demonstrates \pm 15^\circ angle discrimination in the two bands. To authors' knowledge, this is the first demonstration of an original dual-band CMOS monopulse receiver architecture for angle detection applications. [ABSTRACT FROM AUTHOR]

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP1dB of 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP1dB of up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP1dB of up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm2 chip area including test pads. To the best of the authors’ knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process. [ABSTRACT FROM AUTHOR]

This paper presents a 0.4-V ultra-low power (ULP) third-order active-RC complex band-pass filter (CxBPF) for Bluetooth low energy receivers prototyped in a 180 nm CMOS process. The ULP is reached by using single-stage inverter-based operational transconductance amplifiers (OTA) instead of two or more stages OTA. The effects of the low voltage gain and resistive loading are reduced by using a process and temperature robust negative transconductor connected to the virtual ground. The ultra-low voltage operation is reached by using only two stacked transistors and PMOS bulk forward bias. The CxBPF operates well down to 0.4V power supply and the experimental results present power dissipation of only $10.9~\mu \text{W}$ /pole, 1 MHz bandwidth centered at 2 MHz, image rejection rate of 34 dB, and 12.7 fJ FoM. [ABSTRACT FROM AUTHOR]

In this paper, we present a mixer-first receiver front-end suitable for millimeter wave (mm-wave) applications. The proposed architecture includes a modified single-balanced mixer core with an on-chip balun in order to provide a differential output from an injected single-ended local oscillator signal. The mm-wave active balun incorporates a cascode cross-coupled structure to achieve a high voltage gain with low amplitude and phase imbalance. The inter-stage inductors are utilized to increase the mixer conversion gain (CG). Moreover, by manipulating the transistor body effect in the transconductance stage, the CG and noise figure of the mixer are further improved. The mixer also achieves a high input return loss which makes it suitable for the mixer-first receivers. As a proof-of-concept, a 53–67 GHz mixer with a center intermediate-frequency of 20 GHz is designed and implemented in a 65-nm CMOS process. The mixer achieves a measured peak conversion gain of 12.1 dB and a 1-dB compression point of −5 dBm. Furthermore, the fabricated mixer achieves a minimum double-sideband (DSB) noise figure of 6.5 dB over its bandwidth. The whole chip consumes 11.5 mW from a 1-V supply and excluding the pads occupies 0.27 mm2 of silicon area. [ABSTRACT FROM AUTHOR]

For spaceborne instrumentation, the prohibitive cost of a flight traditionally favors programmable solutions such as field programmable gate arrays (FPGAs). As scientific goals become more ambitious, the FPGA-based solutions are showing limitations, especially with restricted launch vehicle capacity and available solar power. In this paper, modern integrated circuit technology is adopted to realize two fully integrated spectrometer SoCs to support spaceborne telescopic sensing. The system specifications are derived from the scientific principles of radio-frequency spectroscopy while each component strives for a simple and reliable implementation. Realized in 65-nm CMOS technology, Design A operates at 2.6 GHz with a three-bit ADC, a 2048-point FFT with 8192-point polyphase filter bank, and a billion-count accumulator. Design B more than doubles the bandwidth, reaches 6 GS/s by interleaving the ADC. The FFT size is also quadrupled to 8192. Both designs include integrated phase locked loops and tunable clock distribution networks. Design A consumes a peak power of 650 mW and Design B consumes 1.5 W. They represent the highest level of integration among similar endeavors and achieve orders of magnitude of improvement over traditional solutions in terms of size, weight, and power consumption. Both designs are actively involved in NASA’s spectroscopy missions. [ABSTRACT FROM AUTHOR]

A feedforward linearization technique for third-order intermodulation (IM3) distortion cancellation in active downconversion mixers is proposed in this paper. Low-frequency second-order intermodulation (IM2) tones are created and multiplied with the mixer’s output to generate low-frequency IM3 replicas for cancellation. Implemented mostly at the IF band, this technique brings a third-order input intercept point (IIP3) improvement independently of the mixer topology and is robust against parasitic parameters. A 2-GHz current commutating mixer linearized by the proposed technique is designed and fabricated using a 130-nm CMOS process to verify the concept. Experimental results show that the mixer with a unit-gain amplifier delivers 8.5 dB of conversion gain and has an IIP3 of 2.5 dBm before linearization. The linearization technique improves the mixer’s IIP3 by 12 dB for input signals as large as −15 dBm. The technique has a negligible impact on the mixer’s gain and incurs a noise figure penalty of less than 0.2 dB. The mixer with the unit-gain amplifier consumes a current of 8.4 mA, while the proposed technique circuitry consumes an extra current of 4.2 mA, both using a 1.2-V voltage supply. [ABSTRACT FROM AUTHOR]

For a coded massive multi-user multiple-input multiple-output (MIMO) system, a soft-output MIMO detector is essential since it can provide a significant coding gain, e.g., 3 dB, compared with a hard-output detector. However, the computational complexity of the soft-output MIMO detector is usually much greater than that of the hard-output detector. This paper presents the first soft-output message-passing detector (MPD), which is also integrated with a high-throughput polar decoder. The algorithm and architecture are designed concurrently to improve the hardware performance. The proposed techniques, including the adaptive variance estimation and reliable symbol detection, reduce the complexity of the MPD by 98.3%, and enable soft output for the outer polar decoder. Compared to the state-of-the-art hard-output design, the proposed MPD achieves a $5.86\times $ higher throughput-to-area ratio (TAR) with 54.3% lower energy dissipation, despite the soft output. The proposed bidirectional-propagation belief propagation decoder is devised to reduce the critical path and to increase the throughput. The proposed polar decoder can improve the TAR by 35% with a comparable area and energy compared with the state-of-the-art polar decoder. A polar-coded massive MIMO receiver that supports a length-1024 rate-1/2 polar code, 128 receive antennas, and eight users is designed and implemented, and delivers a throughput of 7.61 Gb/s. [ABSTRACT FROM AUTHOR]

Power amplifier (PA) nonlinearity and in-phase and quadrature-phase (I/Q) imbalance are major concerns for wireless transmitters. In this paper, we present a new closed-form expression for the probability density function (PDF) of I and Q components in the presence of transmitter’s impairments and propose a blind post-compensation approach for the mitigation of these impairments. These impairments include static PA nonlinearity and frequency-independent I/Q imbalance. The accuracy of the analytical PDF is evaluated using Kullback–Leibler divergence and Hellinger square distance. Simulation results show a reasonable correspondence between the derived PDF and non-parametric kernel density estimation-based PDF. After a closed-form PDF is obtained, higher order statistics-based method is used to estimate PA nonlinearity in the presence of I/Q impairments. Finally, a maximum-likelihood estimation of I/Q imbalance parameters is obtained using the analytical PDF. Simulation results show a normalized mean-squared error (NMSE) of around −40 dB and an adjacent channel power ratio of around −53 dBc, along with an error vector magnitude (EVM) of around 1%, for a 3-MHz local thermal equilibrium signal. Using laboratory measurements, an NMSE of around −35 dB and an EVM of 1.5% are achieved. [ABSTRACT FROM AUTHOR]

This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offset frequency, and the measurements indicate a significant improvement in the overall front-end interference robustness, while sensitivity remains unaffected. To optimize notch performance, the BB impedance is analyzed in detail. The front-end RF range is 750 MHz–3 GHz with an RF channel bandwidth of 20 MHz corresponding to 10-MHz BB bandwidth. The notch frequency is programmable from 16, which is less than one octave from the channel edge, up to 160 MHz. The gain-compression improvement is upto 9 dB, while IIP2 can be increased by more than 26 dB without calibration and IIP3 is 1 dBm. The current overhead for the notch function is between 7.5 and 30 mA, but it only exists under strong blocker conditions as the notch filter can be switched OFF if strong blockers are absent. The total front-end current consumption excluding the notch filter varies with LO frequency from 31 to 44 mA from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

In this paper, we analyze a mixer-first receiver, which includes passive polyphase mixers, low-noise baseband amplifiers, and baseband circulant-symmetric polyphase feedback. This analysis is performed for input frequencies located around any harmonic frequency of the local oscillator. From this, circuits and methods are introduced, which allow control of the receiver’s harmonic input impedance through the use of resistive–capacitive ($RC$) baseband feedback networks. We show that the harmonic input admittance of the mixer-first receiver is related to the discrete Fourier transform of the baseband circulant. This Fourier relationship allows control of the harmonic impedance response across frequencies. The noise figure of the receiver with circulant-symmetric feedback can approach that of an equivalent mixer-first receiver having harmonic feedforward cancelation without the additional power consumption of a cancelation stage. Harmonic impedance shaping can improve the blocker tolerance by decreasing the harmonic conversion gain. A single design can be reconfigured to use these techniques for fundamental-frequency or subharmonic operation. Derivations for impedance, conversion gain, and noise figure are included and a linear time-invariant circuit model is introduced. These are validated through circuit simulation using a combination of 45-nm silicon-on-insulator CMOS technology and behavioral baseband models. [ABSTRACT FROM AUTHOR]

This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The proposed 64-tapped adaptable-delay-line-based design is intended as a high-rate oversampling baseband binary quantizer for a high-speed serial link. The data-receiver has been demonstrated to digitize up to 25-Gb/s input binary symbol sequences with an oversampling ratio of eight. Designed in a 45-nm SOI CMOS process, the receiver circuit is fully characterized by applying different symbol sequences at its input while setting its time resolution and dynamic-range/delay to 5 and 320 ps, respectively. Under these conditions, the data-receiver consumes 270 mW of power, and achieves an energy conversion figure of 1.62–4.32 pJ/sampled-digital-bit. The circuit occupies 0.24 mm2 of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far. [ABSTRACT FROM AUTHOR]

Linear periodically time-varying (LPTV) circuits are finding increased prominence in reconfigurable transceiver applications. Impedance matching of such circuits to the antenna impedance is essential for fully on-chip receiver topologies. However, deriving the $S_{11}$ of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also be expected due to the time-varying nature of the circuit. This paper utilizes the conversion matrix-based analysis technique to compute the $S_{11}$ of a general LPTV circuit. Furthermore, it is shown that signal reradiation at harmonic shifts from input frequencies is also obtained as a natural consequence of this analysis. Examples related to mixer-first receivers, switched-capacitor receiver front-ends (with reset), and Filtering-by-Aliasing (FA)-based receivers are considered to verify the analysis. Design guidelines are provided to attain optimal $S_{11}$ in a few such scenarios. Explicit analytical expressions are derived for reradiation in ideal $N$ -path mixer-first receivers and FA-based receivers, while guidelines are provided for proper choice of conversion matrix expressions/sizes in case of numerical computation. [ABSTRACT FROM AUTHOR]

This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process. [ABSTRACT FROM AUTHOR]

MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high fT HBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core. [ABSTRACT FROM AUTHOR]

In this paper, we combine practically verified results from circuit theory with communication-theoretic laws. As a result, we obtain closed-form theoretical expressions linking fundamental system design and environment parameters with the power consumption of analog front ends (AFEs) for communication receivers. This collection of scaling laws and bounds is meant to serve as a theoretical reference for practical low power AFE design. We show how AFE power consumption scales with bandwidth, SNDR , and SIR. We build our analysis based on two well established power consumption studies and show that although they have different design approaches, they lead to the same scaling laws. The obtained scaling laws are subsequently used to derive relations between AFE power consumption and several other important communication system parameters, namely, digital modulation constellation size, symbol error probability, error control coding gain, and coding rate. Such relations, in turn, can be used when deciding which system design strategies to adopt for low-power applications. For instance, we show how AFE power scales with environment parameters if the performance is kept constant and we use these results to illustrate that adapting to fading fluctuations can theoretically reduce AFE power consumption by at least 20x. [ABSTRACT FROM AUTHOR]