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A 6.78 MHz single-stage transmitter (TX) using a reconfigurable regulating class-D power amplifier (PA) for wireless power transfer (WPT) applications is presented. Based on a 3-mode modulation scheme, the TX achieves power regulation and transmission with only one power stage. A discontinuous-conduction-mode (DCM) zero-voltage switching (ZVS) scheme is adopted to reduce switching loss. A control loop is set to regulate the output voltage of the WPT receiver (RX) by automatically adjusting the transmitting power. With dual-loop control and a proportional-integral (PI) compensation scheme, the loop achieves tight regulation and fast response. The controller is implemented digitally to benefit from the AirFuel® embedded Bluetooth communication link. The PA was fabricated with a high-voltage 0.35 μm CMOS process, and the digital controller with a standard 0.35 μm CMOS process, respectively. Measurement results show that the output voltage of the RX was correctly regulated to 11.7 V under a load change of 50mA to 500mA, and the WPT system could deliver a maximum power of 7.3 W to the RX over a distance of 4.0 cm, and achieved TX to RX peak efficiency of 57.3%. [ABSTRACT FROM AUTHOR]

This article presents a dual-vector distributed beamformer architecture that employs a series-feed network and is capable of supporting up to four simultaneous beams. The multibeam array uses scalar functions within each front end to create Cartesian-weighted signals needed for phase shifting. A dual-vector series-feed network combines/distributes these signals for the receiver/transmitter whereas a global quadrature interpolator is used to create two conjugate beams. By using an interpolator on either end of the series feed, a total of four beams can be obtained. Among these four beams, a first beam can be controlled independently, a second beam is formed as an image of the first, a third beam is offset from the first based on the amount of phase shift within the series-feed structure, and a fourth beam is an image of the offset beam. In this work, the theory of operation of the series-feed DVDB is presented and then two different four-element 28 GHz DVDB transceiver array prototypes in 120 nm SiGe BiCMOS technology are described. One uses a hybrid coupler for global interpolation at radio frequency (RF) and the other uses quadrature mixers for global interpolation at baseband. Measurement results for the array employing passive interpolation at RF show excellent phase-shifting performance, including < 1 dB root-mean-squared (RMS) gain error, < 2 degree RMS phase error, 24% 3 dB bandwidth, with 16–18.6 dBm saturated output power in transmit mode and 4.9–7.3 dB noise figure in receive mode. Measurement results for the array employing mixer-based interpolation likewise show excellent phase-shifting performance with similar RMS gain and phase errors and slightly degraded overall RF performance. Comparing the two, we conclude that the DVDB with passive interpolation at RF is better suited for partitioned systems where beamformers and transceivers are realized on separate chips to support larger, scalable arrays. In contrast, the DVDB with mixer-based interpolation is better suited for integrated systems where beamformers and frequency translation functions must be integrated together. [ABSTRACT FROM AUTHOR]

This article proposes a power scalable beam-oriented digital predistortion (PSBO-DPD) architecture suitable for linearizing PAs in compact hybrid massive multiple-input multiple-output (MIMO) transmitters, without the need to implement a dedicated observation path for each PA. Based on an assumption that all PAs are similar, the feedback configuration for only one PA is sufficient to acquire the nonlinear information of PAs in a given subarray, which are driven at different power levels due to amplitude beamforming. Therefore, the PSBO-DPD resolves the deficiency of current DPD techniques in hybrid beamforming array by estimating the output signal of each PA from the only captured output signal from one PA to construct the main beam signal of the subarray. The predistorter is identified based on the estimated main beam signal and the input signal driving the subarray. To estimate the outputs of each PA efficiently, a power scalable cascade PA model is proposed to reduce the computational complexity and associated overhead in terms of cost and energy consumption. Measurements on a 4-element antenna array with up to 100 MHz bandwidth signal are carried out to validate and bench mark the proposed PSBO-DPD against the existing DPD technique in hybrid massive MIMO transmitters. [ABSTRACT FROM AUTHOR]

A splitting frequencies-based wireless power and information simultaneous transfer (SF-WPIT) method is proposed, and its power and information transfer performances are investigated theoretically and experimentally. First, the power and information transfer characteristics, including transmitting power, power efficiency, frequency bandwidth, and effective operating range, are investigated theoretically on the splitting frequencies of strongly coupled region in symmetric series–series resonant inductive link. The investigation result shows that the splitting frequencies have a good potential of realizing a high-performance power and information transfer. Second, the SF-WPIT system is configured and the factors that influence on the performance of this system are investigated theoretically. A method of tracing two splitting frequencies is presented. A response time calculation method of splitting frequencies is presented, and the influence of response times on the performance of the SF-WPIT system is clarified. Finally, an experimental prototype is constructed with a pair of planar coils of 75-mm mean radius, and the proposed theory and system performance are verified by experimental results. This prototype exhibits a 15 kb/s of data rate and a stable power transfer irrespective of distance change in its operating range of 0–120 mm. [ABSTRACT FROM AUTHOR]

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal envelope. Compared to a digital-quadrature TX architecture this results in a significantly reduced average and peak RF-DAC cell utilization. Therefore, the RF-DAC can be operated in less back-off at higher average output power and drain efficiency. The phase modulation is constrained in order to relax the phase modulators system requirements. Compared to a digital polar TX architecture utilizing an RF digital phase-locked loop with two-point phase modulation, this results in reduced frequency modulation and digital-controlled oscillator tuning range requirements. In addition, the design effort is further shifted from analog to digital domain in order to better exploit the benefits of CMOS technology scaling. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated RF-powered temperature sensor with non-intermittent operation. The sensor is powered up wirelessly from a 915-MHz incident signal using a power-efficient RF energy harvester, uses a subthreshold ring oscillator that produces a highly temperature-dependent oscillation frequency acting as a temperature-to-frequency converter, and finally transfers the frequency-modulated signal to an external reader using back scattering. The power management circuits are eliminated in the designed sensor to arrive at a minimalistic design. For proper operation, a novel voltage regulator is developed that produces a relatively constant output voltage as the supply voltage of the ring oscillator for a large range of harvested input energy but allows the output voltage to change as a function of the temperature for added temperature sensitivity of the overall sensor. Power consumption of the proposed sensor is only 1.05~\mu\textW at room temperature, which enables continuous operation of the sensor from an incident energy of −16 dBm. The sensor is tested between −10 °C to 100 °C exhibiting a minimum sensitivity of 238 Hz/°C at −10 °C and a maximum sensitivity of 31.648 kHz/°C at 100 °C. The predicted temperature error is −2.6 °C to 1.3 °C using a two-point calibration within the range of 10 °C to 100 °C. With a conversion time of 25 ms, 0.046 °C (rms) resolution is achieved. Fabricated in IBM’s 130-nm CMOS technology, the proposed sensor occupies a die area of 0.23 mm2. [ABSTRACT FROM PUBLISHER]