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This paper focuses on the distributed consensus seeking of multi-agent systems (MASs) with discrete-time control updating and intermittent communications among agents. Compared with existing linearly coupled protocols, a nonlinear coupled Zeno-free event-triggered controller is first proposed, which is further to project the static and dynamic triggering mechanisms exploited by using the deadband control method. Then, the node-based nonlinear coupled adaptive event-triggered controller with online self-tuning of time-varying coupling weight and its corresponding to static and dynamic deadband-based event-triggered mechanisms are designed, respectively. The exploited adaptive event-triggered controller does not rely on any global information of interaction structure and is implemented in a fully distributed fashion. In addition, two dynamic proposals not only cover existing static strategies as special cases, but also show that the minimal inter-execution time of dynamic one is not smaller than that of static one. Theoretical analysis shows that the proposed static and dynamic deadband-based event-triggered mechanisms can not only ensure the average consensus with Zeno-freeness, but also achieve the data reduction of communication and control. Finally, the proposed algorithms applied to circuit implementation are corroborated to prove its practical merits and validity. [ABSTRACT FROM AUTHOR]

Passively-integrated memristors are the most prospective candidates for designing high-speed, energy-efficient, and compact neuromorphic circuits. Despite all the promising properties, experimental demonstrations of passive memristive crossbars have been limited to circuits with few thousands of devices until now, which stems from the strict uniformity requirements on the IV characteristics of memristors. This paper expands upon this vital challenge and investigates how uniformity impacts the computing accuracy of analog memristive circuits, focusing on neuromorphic applications. Specifically, the paper explores the tradeoffs between computing accuracy, crossbar size, switching threshold variations, and target precision. All-embracing simulations of matrix multipliers and deep neural networks on CIFAR-10 and ImageNet datasets have been carried out to evaluate the role of uniformity on the accuracy of computing systems. Further, we study three post-fabrication methods that increase the accuracy of nonuniform 0T1R neuromorphic circuits: hardware-aware training, improved tuning algorithm, and switching threshold modification. The application of these techniques allows us to implement advanced deep neural networks with almost no accuracy drop, using current state-of-the-art analog 0T1R technology. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of event-triggered optimized control for uncertain nonlinear Itô-type stochastic systems with time-delay and unknown dynamic. By using fuzzy logic systems to approximate two unknown nonlinear functions with the delayed state and current state, respectively. The adaptive identifier is constructed to determine the stochastic system, and the optimized control is designed by using the identifier and adaptive dynamic programming (ADP) of actor-critic architecture. Almost all of the works are concentrated on ADP-based optimal control and it will inevitably cause the complexity of computation and requirements of persistence excitation (PE) assumption. In this paper, the ADP algorithm is obtained based on the negative gradient of a simple positive function (equivalent to the HJB equation), and so the proposed optimal control is simple and can release the PE assumption. Moreover, the event-triggered control approach is proposed to reduce computing burden and communication resources. Furthermore, we prove that the states of system and FLSs parameter errors are semi-globally uniformly ultimately bounded (SGUUB) in mean square via the adaptive identifier and the Lyapunov direct method as well as identifier-actor-critic architecture-based ADP algorithm. Finally, the effectiveness of the proposed method is illustrated through two numerical examples. [ABSTRACT FROM AUTHOR]

This paper aims to refine and expand the theoretical and application framework of higher-dimensional digital chaotic system (HDDCS). Topological mixing for HDDCS is strictly proved theoretically at first. Topological mixing implies Devaney’s definition of chaos in a compact space, but not vice versa. Therefore, the proof of topological mixing promotes the theoretical research of HDDCS. Then, a general design method for constructing HDDCS via loop-state contraction algorithm is given. The construction of the iterative function uncontrolled by random sequences (hereafter called iterative function) is the starting point of this research. On this basis, this paper put forward a general design method to solve the construction problem of HDDCS, and several examples illustrate the effectiveness and feasibility of this method. The adjacency matrix corresponding to the designed HDDCS is used to construct the chaotic Echo State Network (ESN) for predicting Mackey-Glass time series. Compared with other ESNs, the chaotic ESN has better prediction performance and is able to accurately predict a much longer period of time. [ABSTRACT FROM AUTHOR]

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC. [ABSTRACT FROM AUTHOR]

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. [ABSTRACT FROM AUTHOR]

The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization. [ABSTRACT FROM AUTHOR]

Since chaotic cryptography has a long-term problem of dynamic degradation, this paper presents proof that chaotic systems resist dynamic degradation through theoretical analysis. Based on this proof, a novel one-dimensional two-parameter with a wide-range system mixed coupled map lattice model (TWMCML) is given. The evaluation of TWMCML shows that the system has the characteristics of strong chaos, high sensitivity, broader parameter ranges and wider chaos range, which helps to enhance the security of chaotic sequences. Based on the excellent performance of TWMCML, it is applied to the newly proposed encryption algorithm. The algorithm realizes double protection of private images under the premise of ensuring efficiency and safety. First, the important information of the image is extracted by edge detection technology. Then the important area is scrambled by the three-dimensional bit-level coupled XOR method. Finally, the global image is more fully confused by the dynamic index diffusion formula. The simulation experiment verified the effectiveness of the algorithm for grayscale and color images. Security tests show that the application of TWMCML makes the encryption algorithm have a better ability to overcome conventional attacks. [ABSTRACT FROM AUTHOR]

In this paper, a unified framework is proposed to address the synchronization problem of memristor chaotic systems (MCSs) via the sliding-mode control method. By employing the presented unified framework, the finite-time and fixed-time synchronization of MCSs can be realized simultaneously. On the one hand, based on the Lyapunov stability and sliding-mode control theories, the finite-/fixed-time synchronization results are obtained. It is proved that the trajectories of error states come near and get to the designed sliding-mode surface, stay on it accordingly and approach the origin in a finite/fixed time. On the other hand, we develop an image encryption algorithm as well as its implementation process to show the application of the synchronization. Finally, the theoretical results and the corresponding image encryption application are carried out by numerical simulations and statistical performances. [ABSTRACT FROM AUTHOR]

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced March algorithm is designed to detect all the modeled faults. In one resistor crossbar with $N$ memristors, the enhanced March algorithm requires $8N$ write and $7N$ read operations with negligible hardware overhead. To reduce the test time, a March RC algorithm is proposed based on read operations with new reference currents, which requires $4N+2$ write and $6N$ read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement March RC algorithm with a little area overhead. [ABSTRACT FROM AUTHOR]

Blockchain distributed ledger technology (DLT) has widespread applications in society 5.0 because it improves service efficiency and significantly reduces labor costs. However, employing blockchain DLT entails considerable energy consumption in the mining process. This paper proposes a blockchain accelerator (BCA) with ultralow power consumption and a high processing rate to address the problem. The BCA focuses on accelerating the double secure hash algorithm (SHA) 256 function required in the mining process at a system-on-chip (SoC) level. We propose three ideas, namely, multiple local memories (multimem), double-cell processing element (D-PE), and nonce autoupdate (NAU), to reduce the external data transfer time and improve the BCA hardware efficiency. We propose a cascaded multiple BCA chip model to enhance the system throughput by several-fold. Our experiments on an ASIC and FPGA prove that the proposed BCA successfully performs the mining process for multiple blockchain networks with much lower power consumption than that of the state-of-the-art CPUs and GPUs. The BCA is laid out with Renesas 65 nm technology with a chip area of $25~mm^{2}$ and consumes $530~mW$ at 100 MHz. The power efficiency of the layout chip is improved by 2428 and 143 times compared with that of the fastest CPU Intel i9-10940X and GPU RTX 3090, respectively. [ABSTRACT FROM AUTHOR]

This paper addresses the finite-time and fixed-time bipartite average tracking (BAT) problems in multi-agent systems (MASs) subject to bounded disturbances. A novel non-smooth protocol is first constructed on the basis of utilizing the finite-time control method, which can realize the finite-time BAT with structurally balanced graph. Then, the fixed-time BAT problem is dealt with nonlinear fixed-time algorithm, the setting time of which is obtained without depending on initial states. By employing Lyapunov stability theory, some sufficient criteria are obtained to achieve the finite-time and fixed-time BAT for MASs with disturbances. Numerical examples are finally developed for illustration. [ABSTRACT FROM AUTHOR]

This paper presents a novel hardware architecture of the Tensorial Support Vector Machine (TSVM) based on Shallow Neural Networks (NN) for the Single Value Decomposition (SVD) computation. The proposed NN achieves a comparable Mean Squared Error and Cosine Similarity to the widely used one-sided Jacobi algorithm. When implemented on an FPGA, the NN offers $324\times $ faster computations than the one-sided Jacobi with reductions up to 58% and 67% in terms of hardware resources and power consumption respectively. When validated on a touch modality classification problem, the NN-based TSVM implementation has achieved a real-time operation while consuming about 88% less energy per classification than the Jacobi-based TSVM with an accuracy loss of at most 3%. Such results offer the ability to deploy intelligence on resource-limited platform for energy-constrained applications. [ABSTRACT FROM AUTHOR]

Piecewise affine (PWA) systems are attractive models that can represent various hybrid systems with local affine subsystems and polyhedral regions due to their universal approximation properties. The identification problem of PWA systems amounts to estimating the number of subsystems, parameters of each subsystem, and the corresponding polyhedral partitions via state-input vectors. In this paper, we propose a novel approach to address the online identification problem of continuous-time PWA systems in state-space form. Specifically, an online active mode recognition algorithm and a generalized integral concurrent learning identifier are presented to acquire the number of subsystems, the switching sequence, and the parameter of each subsystem. In addition, we develop the optimization problem for the polyhedral partition estimation, which is solved by using the estimated switching sequence and subsystem parameters. The effectiveness of the proposed identification approach is demonstrated via simulation results. [ABSTRACT FROM AUTHOR]

Deep Neural Networks (DNNs) are increasingly being used in a variety of applications. However, DNNs have huge computational and memory requirements. One way to reduce these requirements is to sparsify DNNs by using smoothed LASSO (Least Absolute Shrinkage and Selection Operator) functions. In this paper, we show that irrespective of error profile, the sparsity values obtained using various smoothed LASSO functions are similar, provided the maximum error of these functions with respect to the LASSO function is the same. We also propose a layer-wise DNN pruning algorithm, where the layers are pruned based on their individual allocated accuracy loss budget, determined by estimates of the reduction in number of multiply-accumulate operations (in convolutional layers) and weights (in fully connected layers). Further, the structured LASSO variants in both convolutional and fully connected layers are explored within the smoothed LASSO framework and the tradeoffs involved are discussed. The efficacy of proposed algorithm in enhancing the sparsity within the allowed degradation in DNN accuracy and results obtained on structured LASSO variants are shown on MNIST, SVHN, CIFAR-10, and Imagenette datasets and on larger networks such as ResNet-50 and Mobilenet. [ABSTRACT FROM AUTHOR]

The supersingular isogeny key encapsulation (SIKE) protocol, as one of the post-quantum protocol candidates, is widely regarded as the best alternative for curve-based cryptography. However, the long latency, caused by the serial large-degree isogeny computation which is dominated by modular multiplications, has made it less competitive than most popular post-quantum candidates. In this paper, we propose a high-speed and low-latency architecture for our recently presented optimized SIKE algorithm. Firstly, we design a new field arithmetic logic unit (FALU) with many algorithmic transformations and architectural optimizations. Especially, for the FALU, an extremely low-latency modular multiplier is devised based on a modified algorithm by fully parallelizing and highly optimizing the small-size multipliers and the reduction submodules. Secondly, we develop a compact control logic and update the instructions based on the benchmark provided in the newest SIKE library, fitting well with our design. Thirdly, an efficient memory access method is proposed by scheduling the input and output of the arithmetic logic unit (ALU) in two identical RAMs, which can significantly reduce the latency. Finally, we code the proposed architectures using the Verilog language and integrate them into the SIKE library. The implementation results on a Xilinx Virtex-7 FPGA show that for SIKEp751, our design only costs 9.3 ms with a frequency of 155.8 MHz, about 2× faster than the state-of-the-art, and achieves the best area efficiency among existing works. Particularly, the modular multiplier merely needs 16 clock cycles, reducing the delay by nearly one order of magnitude with a small factor of increase in hardware resource. [ABSTRACT FROM AUTHOR]

This paper is concerned with the almost sure exponential synchronization of a multilayer network which is set up on a non-strongly connected digraph that can be classified into several layers by Tarjan’s algorithm. Note that, in the multilayer network, white-noise-based time-varying coupling and drift term coupling are proposed to simulate two kinds of coexisting distinguishable interactions between vertices. We develop a normal analytical framework for studying synchronization of the multilayer network. Firstly, via aperiodically intermittent pinning noises, synchronization of vertices situated on the first layer is achieved in the layered network. Secondly, under the impact of the white-noise-based time-varying coupling in diffusion term, synchronization of the vertices located in other layer networks is developed with the support of synchronization for the pinned vertices. Employing Lyapunov method, graph theory and stochastic analysis technique, a criterion of almost sure global exponential synchronization is obtained. By adopting the concepts of average noise control rate and average noise control period proposed recently, we lessen the conservativeness of the conditions restricted on aperiodically intermittent noise control to optimize our results. Furthermore, an application to a class of Chua’s circuits is exhibited in detail. In the end, we provide a numerical example to verify the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm2 area consumption. [ABSTRACT FROM AUTHOR]

This paper proposes two kinds of algorithms to achieve privacy-preserving consensus of multi-agent systems over undirected graphs via node decomposition mechanism and homomorphic cryptography technique. Based on the number of neighboring nodes (|Ni|), every agent is decomposed into |Ni| subagents, which are connected as a chain graph. Note that every subagent connects one and only one non-homologous subagent (generated by different agents). Information interaction between non-homologous subagents is encrypted by a homomorphic cryptography algorithm, and homologous subagents exchange information directly. In this regard, the proposed node decomposition mechanism enhances the privacy of the initial values without increasing the computational complexity of encryption. The first privacy-preserving algorithm can achieve the accurate average consensus, which means that the agreement value of every subagent is consistent with the original average consensus value. The second algorithm studies the privacy-preserving scaled consensus problem without a priori knowledge about the underlying graph. Although the final convergence values of subagents do not keep exactly the same, homologous subagents can compute the original group decision value by resorting to the product of the limit value and agent’s degree. Importantly, this algorithm also guarantees the privacy of group decision value of the whole system. Besides, it is proved that the privacy of the initial value can be preserved if the agent has at least one neutral neighbor. [ABSTRACT FROM AUTHOR]

This article proposes a robust method for the synthesis and design of optimal linear group delay filters with prescribed bandwidth and dispersion properties. The proposed filters are based on a cascade of second-order all-pass filter cells, for which all the parameters are optimized in order to reach the desired wideband linear group delay characteristic with positive slope. Compared to the previously published synthesis method, the proposed approach offers appropriate initialization enabling convergence and aiming for the optimal solution. The method’s convergence and robustness are proved through a 21-cells synthesis, which is the highest number of cascaded cells reported to date, due to the usual convergence problem. Then the electronic feasibility is illustrated through the measurement results of a lumped-elements linear group-delay filter prototype dimensioned with this method. The measured group delay presents a positive slope of 8 ns GHz−1 in the frequency range [100–725] MHz. It is, to the best of our knowledge, the highest positive slope reported to date with an electronic implementation (i.e except SAW and waveguide devices). [ABSTRACT FROM AUTHOR]

We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication. [ABSTRACT FROM AUTHOR]

A multi-purpose mechanical platform to track moving objects in three-dimensional space has been developed. It is composed of one main microcontroller board that processes all system data, two cameras, three motors, and one secondary microcontroller board to position a platform with three degrees of freedom. The system computes the optical flow and moves the cameras accordingly, tracking motion within the visual scene. The platform operates autonomously. To the best of our knowledge, there are no similar systems reported with low-resolution image sensors and low-cost microcontrollers. Existing solutions rely on personal computers and advanced FPGAs to process image data. This article concludes that the optical flow operation is efficient even using an image sensor with very low resolution. Thus, the system complexity and image data processing are alleviated significantly. The platform can be easily adapted to different application scenarios by adding new peripherals, sensors, or image processing algorithms. A detailed description of the system design and experimental results are provided. [ABSTRACT FROM AUTHOR]

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm. [ABSTRACT FROM AUTHOR]

The convergence of the waveform relaxation (WR) method is demonstrated for a class of circuits: Chains of identical and symmetrical passive subcircuits. The WR algorithm uses resistive coupling to implement the iteration. Every part is modeled as a symmetric and reciprocal linear two-port network. The iteration matrices of the WR operator are constructed for the Gauss-Jacobi and Gauss-Seidel relaxations in the Fourier domain. An upperbound estimate of the spectral radius of the WR operator is presented. It demonstrates the convergence of the method independently of the number of cascaded parts in the chain and the coupling resistance. [ABSTRACT FROM AUTHOR]

The TICER (TIme-Constant Equilibration Reduction) algorithm is a well-known resistor-capacitor (RC) network reduction algorithm. It finds wide applications in integrated circuit post-layout simulation tools. However, the original algorithm is one-dimensional in that each step eliminates one circuit node to obtain an approximately equivalent circuit by connecting additional elements to the neighboring nodes after each elimination. This work extends the TICER algorithm to its high-dimensional version in the sense that each step eliminates a subcircuit as a whole to obtain an approximately equivalent circuit, again by connecting extra elements to the neighboring nodes after each elimination. In practice the high-dimensional TICER (HD-TICER) algorithm finds many advantages over the classical one-dimensional TICER (1D-TICER) algorithm, which is a special case of the HD-TICER algorithm. An elegant mathematical derivation of the HD-TICER algorithm is provided by applying the notion of driving point impedance (DPI). The advantages of the HD-TICER algorithm are demonstrated by application to reductions of some purely resistive networks and RC networks. An approximate time constant estimation method is also provided for selection of a subblock circuit to eliminate. [ABSTRACT FROM AUTHOR]

Stereo vision is widely deployed on robots and drones to enable depth estimation at a low cost. The combination of lightweight deep neural network (DNN) and cost volumes algorithm is proved to possess the advantages of both high depth estimation accuracy and speed. However, currently there is no accelerator architecture compatible with both efficient DNN inference and cost generation algorithms such as stereo matching. This work proposes a stereo vision accelerator called Dadu-eye, dedicated to real-time processing of high-resolution image streams. The proposed architecture adopts a pipelined hardware design with the techniques of operation approximation and scheduling-level optimization. First, a cost estimation block is designed to generate cost volumes from both luminance and color information. Second, a super pipelined multiplication and accumulation array with a row scan-based fused-layer convolution scheduling is proposed to perform the encoding and decoding neural network efficiently. Finally, an optical flow block is designed and cooperates with the array to approximately predict half of the frames’ depth to achieve real-time (30fps) processing on 1080p view. Based on the SMIC 40 nm CMOS process, this stereo vision accelerator achieves 5.3 TOPS/W power efficiency and significantly reduces 81% off-chip memory access. [ABSTRACT FROM AUTHOR]

When the accumulated zero-mean output of a digital modulator encounters a nonlinear function, nonlinearity-induced spurs can arise in the spectrum of the resulting signal. These spurs occur with both periodic and aperiodic modulator outputs, and can appear in applications such as frequency synthesis at frequencies where filtering approaches are ineffective. The mechanism at the root of these spurs is the nonlinear transformation of the cyclostationary modulator-induced phase noise. An algorithm is presented which determines modulator parameters that guarantee a spur-free spectrum after the application of a memoryless nonlinearity to the accumulated modulator noise. The algorithm takes as its input a sampled representation of the in-loop nonlinearity function, and determines a matrix of probabilities to be applied by the modulator. The algorithm can handle arbitrary nonlinear functions and relies on straightforward, synthesizable operations. Simulations demonstrate the ability of the algorithm to program a modulator such that spur-free operation is obtained for an illustrative selection of nonlinearities. [ABSTRACT FROM AUTHOR]

Hyperdimensional computing (HDC) is a brain-inspired computing paradigm-based on high-dimensional holistic representations of vectors. It recently gained attention for embedded smart sensing due to its inherent error-resiliency and suitability to highly parallel hardware implementations. In this work, we propose a programmable all-digital CMOS implementation of a fully autonomous HDC accelerator for always-on classification in energy-constrained sensor nodes. By using energy-efficient standard cell memory (SCM), the design is easily cross-technology mappable. It achieves extremely low power, 5 $\mu \text{W}$ in typical applications, and an energy efficiency improvement over the state-of-the-art (SoA) digital architectures of up to $3\times $ in post-layout simulations for always-on wearable tasks such as Electromyography (EMG) hand gesture recognition. As part of the accelerator’s architecture, we introduce novel hardware-friendly embodiments of common HDC-algorithmic primitives, which results in $3.3\times $ technology scaled area reduction over the SoA, achieving the same accuracy levels in all examined targets. The proposed architecture also has a fully configurable datapath using microcode optimized for HDC stored on an integrated SCM-based configuration memory, making the design “general-purpose” in terms of HDC algorithm flexibility. This flexibility allows usage of the accelerator across novel HDC tasks, for instance, a newly designed HDC-algorithm for the task of ball bearing fault detection. [ABSTRACT FROM AUTHOR]

Active noise control (ANC) requires a controller with a small delay. However, in most ANC applications, this delay is significant due to the typically low sample rate, the anti-aliasing (AA), and reconstruction filters (RC) of the analog to digital (AD) and digital to analog (DA) converters. This delay can be reduced by increasing the sampling frequency at the expense of a significant increase in computational complexity. Sigma-delta AD and DA converters work at high sampling frequencies, but their use in ANC is limited due to the delay of AA and RC filters. This work proposes removing the AA and RC filters of the sigma-delta converters and using the oversampled signals directly in an ANC system. This proposal allows the ANC system to be implemented at a large sample frequency but using signals with fewer bits per sample (word-length). This is the first short-word length implementation of the least mean squares (LMS) algorithm to the authors’ knowledge. Gains of up to 6 times may be achieved in the computational complexity when compared with a long-word length implementation. Theoretical and simulation results validate the current solution. [ABSTRACT FROM AUTHOR]

Recurrent Neural Networks (RNNs) have been widely used in many sequential applications, such as machine translation, speech recognition and sentiment analysis. Long Term Short Term Memory (LSTM) and Gated Recurrent Unit (GRU) are widely used variants of RNN due to their effectiveness in overcoming gradient vanishing and exploding problems; however, compared to conventional RNN, their massive storage and computation requirements hinder their application. In addition, the recurrent structure of RNNs makes them prone to accumulate errors, resulting in a severe loss of accuracy. In this work, we propose a hybrid-iterative compression (HIC) algorithm for LSTM/GRU. By exploiting the error sensitivity of RNN, the gating units are divided into error-sensitive and error-insensitive groups, that are compressed using different algorithms. By using this approach, a 37.1 ×/32.3 × compression ratio is achieved with negligible accuracy loss for LSTM/GRU. Further, an energy efficient accelerator for bidirectional RNNs is proposed. In this accelerator, the data flow of the matrix operation unit based on the block structure matrix (MOU-S) is improved through rearranging weights; the utilization of BRAM is improved through a fine-grained parallelism configuration of matrix-vector multiplications (MVMs). Meanwhile, the timing matching strategy alleviates the load-imbalance problem between MOU-S and the matrix operation unit based on top-k pruning (MOU-P). When running at 200MHz on Xilinx ADM-PCIE-7V3 FPGA, the proposed design achieves an improvement in energy efficiency in a range of 5%-237% for LSTM networks, and an improvement of 58% for GRU networks compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Predefined mymargin finite-time output containment control problem for nonlinear multi-agent systems with multiple dynamical leaders under directed topology is investigated, where the outputs of followers can converge to the predefined convex hull formed by the multiple leaders within a finite time, and the leaders can have unknown control inputs. Firstly, for the directed topological structure among the followers, a distributed adaptive observer is designed to estimate the whole states of all the leaders under the influences of the leaders’ unknown inputs. By utilizing Hardy’s inequality and common Lyapunov theory, the finite-time convergence of the proposed observer is proved. On the basis of this conclusion, a predefined distributed containment control protocol including the desired convex combinations of the leaders is developed for each follower by using the given weights. Then an algorithm is proposed to design the control parameters in the proposed containment control protocol. With the help of the output regulation theory, the finite-time output containment criterion for nonlinear multi-agent systems in the presence of the leaders’ unknown inputs is derived. Finally, a numerical simulation example is presented to demonstrate the effectiveness of the theoretical results. [ABSTRACT FROM AUTHOR]