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This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with a time-domain quantizer, the implemented early-late (E/L) detection circuit, the input range is detected to eliminate the unnecessary DAC switching power efficiently. A prototype ADC chip is fabricated in 90 nm CMOS technology with an active area of 0.038 mm2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3~\mu \text W to 2.5~\mu \text W and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

This paper presents a design procedure of high-frequency loosely inductive coupled wireless power transfer (LIC-WPT) system based on class-E^2 dc-dc converter, taking into account the power loss reduction of inverter, coupling part, and rectifier simultaneously. Analytical expressions including the dc-to-dc efficiency of the WPT system are derived and the efficiency deterioration mechanism is explained by the circuit model. Through the analytical expressions, the design procedure for satisfying both the class-E switching conditions and power loss reductions at the coupling part is proposed from the circuit-theory viewpoint. The class-E^2 WPT system designed by the proposed design procedure achieves high dc-to-dc efficiency at low coupling coefficient, in particular, compared with those designed by the previous design strategies. The validity and effectiveness of the proposed design procedure were confirmed by PSpice simulations and circuit experiments. [ABSTRACT FROM PUBLISHER]

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the 3\times\sigma offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 \mum 1P6M CMOS technology, which occupies an active area of only 380\times 430\ \mum^2. At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 \mum CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 \muW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size. [ABSTRACT FROM AUTHOR]

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 \mum CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85\times 0.65\ mm^2. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy is proposed that introduces a switch-driver power consumption aware analysis of the switched current cell. The analysis of the major distortion mechanisms in the switched current cell allows the derivation of a design strategy for maximum linearity. This strategy is extended to include the power consumption of the switch drivers in function of the switched current cell design. To minimize the digital power consumption, low-power implementations of the thermometer decoder and switch driver circuits are introduced. [ABSTRACT FROM PUBLISHER]

The class-E zero-voltage switching/zero-derivative switching operation within class-DE amplifiers can be easily achieved by adding external shunt capacitances. This paper gives the analytical expressions for the designs of the class-DE amplifiers with the shunt capacitances composed of linear and nonlinear capacitances for any grading coefficient m of MOSFET body junction diodes at the switch-on duty ratio D=0.25. In the analysis, an equivalent linear shunt capacitance of the nonlinear MOSFET drain–source parasitic capacitances is derived. Analytical results show good agreements with the simulation and experimental ones, which validate our analysis. [ABSTRACT FROM PUBLISHER]

An analysis of a novel single-ended Class-E mode with shunt capacitance and shunt filter with explicit derivation of the idealized optimum voltage and current waveforms and load-network parameters with their verification by frequency domain simulations with 50% duty ratio is presented. The ideal collector voltage and current waveforms demonstrate a possibility of 100% efficiency. The circuit design with transmission lines at 2.14 GHz is discussed and analyzed. In order to reduce the voltage peak factor, the load network parameters can be rearranged to correspond to Class-E/F 3 mode by providing a short-circuit condition at the third harmonic when the second-harmonic tank is connected in series to the shunt filter. Broadband capability of a Class-E mode with shunt filter using reactance compensation technique has been demonstrated by two examples, one with lumped elements and the other with transmission-line elements. The test board of a transmission-line broadband Class-E GaN HEMT power amplifier with shunt filter was measured and high-performance results with the output power of around 41 dBm, average drain efficiency of 68%, and power gain of about 9 dB were achieved across the frequency band from 1.4 to 2.7 GHz. [ABSTRACT FROM PUBLISHER]

A new switching circuit analysis technique is proposed in which the reverse recovery and junction capacitance non-idealities of diode-based switches are incorporated into a state plane analysis of the circuit. Accurate state plane modeling of the reverse recovery process is based on the development of new generalizations of the classic charge control model. Using as an example a zero-voltage switching dc transformer possessing high sensitivity to diode characteristics, these generalizations are shown to be necessary to achieve accurate results across all operating modes. The proposed circuit analysis technique produces excellent modeling agreement with results measured on a hardware prototype of the dc transformer circuit. [ABSTRACT FROM AUTHOR]