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This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and transfer capacitors to the converter output impedance. As the parasitic capacitances increase, the optimum switching frequency decreases. Secondly, optimum capacitor and switch sizes for maximum efficiency are provided. We show that the overdrive voltage strongly impacts the optimum switch width through the modification of their conductance. To support the sizing methodology, a model of the efficiency of switched-capacitor DC/DC converters is developed. It is validated against simulation and measurement results in 65 nm and 0.13 \mu\ m CMOS, respectively. The proposed sizing methodology shows how the converter efficiency can be traded-off for die area reduction and what is the impact of parasitic capacitances on the converter sizing. [ABSTRACT FROM AUTHOR]

A triple-mode step-up/step-down switched-capacitor DC-DC converter is proposed, and it can work with a wide input voltage range. There are three operational modes in the proposed converter: triple-step-up, double-step-up, and step-down modes. A built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage. The proposed circuit was implemented by a 0.35-\mum CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of 1.56\times 1.47\ mm^2. The output voltage is fixed at 3.3 V, while the input voltage range is 1.8–5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V. [ABSTRACT FROM PUBLISHER]

Charge balance analysis and state transition analysis are presented in analyzing hysteretic voltage mode switching converters working in the steady state. It is shown that the ideal buck converter with a current-sink load can only work in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM), and the same converter with a resistive load can work in CCM, but the output voltage ripple is very large compared to the hysteresis window. Previously published CCM designs are functional because their operations actually rely on the small but nonzero equivalent series resistance (ESR) of the filtering capacitor. For the CCM buck converter with nonzero ESR, our proposed state transition analysis gives a much more accurate switching frequency than previous approaches. The hysteretic voltage mode boost and buck-boost converters are then analyzed, and shown to have no feasible operating region. Crucial simulation results are presented to confirm the analyses. [ABSTRACT FROM PUBLISHER]