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In this paper, we present a reconfigurable Physically Unclonable Functions (PUF) based on the Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM), which exploits thermal noise as the true dynamic entropy source. Therefore, the MRAM cells could be configured to random final states with stochastic switching mechanism. The proposed PUF is constructed and reconfigured by combining the small-capacity true random number generator (TRNG) and high-reliability secure hash algorithm (SHA-512), realizing the dynamic transformation between SOT-MRAM based last level cache and PUF (In-Cache-MPUF). Thanks to the full reconfigurability and the high endurance of SOT-MRAM, the proposed In-Cache-MPUF can achieve $10^{\textbf {14}}$ maximum PUF bits per cell, which has greatly motivated the implementations compared with the traditional weak PUFs utilizing the static entropy source of process variations. The Monte-Carlo simulation results using 40 nm technology and a compact MTJ model show that the proposed PUF has desirable randomness as the digitized bit streams passing all the NIST tests, achieving 50.0428% uniqueness as well as 49.9236% uniformity. It also shows comparable reliability to the state-of-the-art works: a maximum bit error rate of 0.14% and 0.12% at 100 °C and 0.9 V, respectively. In addition, the system level performance is tested and validated by gem5. [ABSTRACT FROM AUTHOR]

With downscaling of process technology, conventional memories encounter challenges, such as soaring static power, low reliability, and charge sharing effect induced by radiation effects. Magnetic random access memory (MRAM) is considered as an outstanding candidate for addressing these challenges. In particular, emerging spin–orbit torque (SOT) MRAMs have shown ultra-fast switching and read-disturbance immunity compared with spin-transfer torque MRAMs. However, the write operation of the SOT-MRAM is more vulnerable to single-event upsets (SEUs) as its ultra-short write pulse is comparable to the radiation current pulse. In addition, its read circuit can also be disturbed by SEUs or even double-node upsets (DNUs) induced by the charge sharing effect. In this paper, we investigate radiation effects on read/write circuits of the SOT-MRAM. Then, we propose novel radiation hardening designs for SOT-MRAM. The hardening technique is first studied at the write circuit by adding six PMOS transistors as a feedback structure to charge/discharge. Afterwards, we propose a radiation hardening read circuit addressing the issue of SEUs and DNUs, which uses redundant six transistors and two feedback connections as the hardening structure. Based on a physics-based SOT magnetic tunnel junction model and a 65-nm complementary metal–oxide–semiconductor design kit, simulation results indicate that radiation-induced soft errors can be corrected at sensitive nodes. Moreover, the error rate of the proposed read circuit is $40\times $ smaller than the previous work, and restoring time is reduced by 30.6% with negligible area overhead. [ABSTRACT FROM AUTHOR]

Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to $0.3~ns$ , and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least. [ABSTRACT FROM AUTHOR]

High capacity last-level caches (LLCs) are being used to help alleviate the growing speed gap between the processor and main memory. However, traditional CMOS based memory technologies (SRAM, DRAM, et al.) for such LLCs consume high static power. Non-volatile memory such as STT-MRAM has been proposed as a low power solution for LLCs. Nevertheless, the high write current induces a so-called “supply current threshold” issue and limits the maximum number of bit-cells that can be written concurrently in one cycle in an STT-MRAM cache. This drawback significantly decreases the bandwidth of the STT-MRAM cache compared with SRAM. In this work, we present a hardware implementation of NAND-like spintronic memory (NAND-SPIN) LLC for the first time. By exploiting the unique erase-then-program operation for writing NAND-SPIN, we propose an adaptive buffer entry (ABE) write policy for each cache write access. Instead of writing a fixed number of bits sequentially, our method adaptively extends the write data length under a fixed maximum cache supply current. Compared to existing STT-MRAM caches, ‘ABE’ can achieve 70% performance improvements on average. Compared with the conventional early write terminate (EWT) policy, ‘ABE’ can save 33% write energy on average with negligible hardware overhead. [ABSTRACT FROM AUTHOR]

Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the bi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational performances. In this paper, we propose a non-volatile cache design based on spin-orbit torque-driven ring-shaped RM. The systematical investigations, covering from device modeling, to circuits design, to bit-cell layout design, and to system evaluation have been carried out. Thanks to the cells-overlapping design, the proposed RM L2 cache can achieve $48\times $ , $16\times $ , and $8\times $ improvements in term of capacity, compared with iso-area caches based on static random access memory (SRAM), spin transfer torque magnetic RAM (STT-MRAM), and tape-shaped RM, respectively. As proved by 4-core system experiment results, the proposed RM cache can improve 30.7% instructions per cycle (IPC) and save 58.2% energy compared with SRAM cache. [ABSTRACT FROM AUTHOR]