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In this paper, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on the high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation) without needing a detailed electrical simulation. Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, MDM Laboratory. The parameters extraction procedure is also discussed. The obtained results clearly show that the model proposed in this paper is able to capture the influence of the programming pulse parameters (i.e. pulse duration and height) changes. This is accomplished by the introduction of a parameter, which is related to the specific device technology. [ABSTRACT FROM AUTHOR]

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies. [ABSTRACT FROM AUTHOR]

This paper proposes a novel approach to build integer multiplication circuits based on speculation, a technique which performs a faster-but occasionally wrong-operation resorting to a multi-cycle error correction circuit only in the rare case of error. The proposed speculative multiplier uses a novel speculative carry-save reduction tree using three steps: partial products recoding, partial products partitioning, speculative compression. The speculative tree uses speculative (m:2) counters, with m>3, that are faster than a conventional tree using full-adders and half-adders. A technique to automatically choose the suitable speculative counters, taking into accounts both error probability and delay, is also presented in the paper. The speculative tree is completed with a fast speculative carry-propagate adder and an error correction circuit. We have synthesized speculative multipliers for several operand lengths using the UMC 65 nm library. Comparisons with conventional multipliers show that speculation is effective when high speed is required. Speculative multipliers allow reaching a higher speed compared with conventional counterparts and are also quite effective in terms of power dissipation, when a high speed operation is required. [ABSTRACT FROM AUTHOR]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus (PLB) architecture by multiplexing each rn-bits onto a single line. This bus architecture, the serial-link bus (SLB), transforms an n-bit conventional PLB into an n/rn-line (serial link) bus. The advantage of SLBs is that they have fewer lines, and if the bus width is kept the same, SLBs will have a larger line pitch. Increasing the line width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing mopt and an optimum width to pitch ratio ηopt exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. The optimum degree of multiplexing and optimum width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology. [ABSTRACT FROM AUTHOR]

To address the von Neumann bottleneck that leads to both energy and speed degradations, in-memory processing architectures have been proposed as a promising alternative for future computing applications. In this paper, we present an in-memory computing system based on resistive random-access memory (RRAM) crossbar arrays that is reconfigurable and can potentially perform parallel and general computing tasks. The system consists of small look-up tables (LUTs), a memory block, and two search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of addition, AND logic and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set consisting of 10 instructions is demonstrated on this architecture through circuit level simulations. Performance evaluations show that the proposed in-memory computing architecture is suitable for handling data-intensive problems. The average power consumption of the crossbar chip is estimated to be $45~\mu \text{W}$. [ABSTRACT FROM AUTHOR]

The AOMedia Video 1 (AV1), developed by the Alliance for Open Media (AOM) industry consortium and released in 2018, is an open-source and royalty-free video coding format. The goal of AV1 is to deliver substantial compression gains over state-of-the-art codecs such as VP9 and HEVC, while keeping a practical decoding complexity, hardware feasibility and an open and free status. This paper presents a high-throughput hardware architecture for ten non-directional AV1 intra prediction modes: DC, Paeth, Smooth, Smooth Vertical, Smooth Horizontal and Recursive-filtering-based modes 0 to 4. The proposed design supports all 19 block sizes specified by AV1 and, in the worst-case scenario, is able to process every single combination of these blocks according to the 10-way partition tree, with a throughput of UHD 4K videos at up to 30 frames per second. When synthesized to the TSMC 40nm cell library targeting a frequency of 648MHz, the proposed design used 128.5K gates and showed a power dissipation and energy consumption per predicted sample of 65.5mW and 0.176pJ/sample, respectively. No other works were found in the literature describing hardware designs for AV1 intra prediction encoder. [ABSTRACT FROM AUTHOR]

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-\mum CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver, the method saves power, even for the worst-case test scenarios. For less demanding conditions, a power saving up to seven times is achieved. The experimental results show significant improvement, in both power saving and dynamic range, compared to the existing adaptation methods. [ABSTRACT FROM AUTHOR]

Most wireless battery-operated devices spend more energy receiving than transmitting. Hence, minimizing the power dissipation in the receiver front end, which, in many cases, is the prominent power consuming part of the receiver, is an important challenge. This paper addresses this challenge by solving two closely related optimization problems. Firstly, we optimize the overall power dissipation in an RF front end consisting of a chain of building blocks to satisfy required overall specifications in gain, linearity and noise figure. We extend this into a second optimization problem, namely to maximize the transmission rate that the receiver can accommodate for a given available receiver battery power budget. In fact, the ratio of this transmission rate vs the available receiver power budget serves as the figure-of-merit that allows a formal optimization where, in particular, the (adjacent channel) interference is a critical factor. Our results include closed-form analytical solutions for certain cases. For high signal power, where the noise is limited by interference, the largest bit/s/Hz per nJ drawn from receiver is reached for a transmission rate of 2.3 bits/s/Hz, irrespective of interference power. Numerical results using practical circuit blocks with 90 nm and 65 nm technologies are in close agreement with the analytical results. [ABSTRACT FROM AUTHOR]

This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 \muA 7–20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240–500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 \mum CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 \muA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/\surdHz IRN density, and occupies 0.21 mm^2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/\surdHz IRN density, and occupies 0.23 mm^2 silicon area without pads. [ABSTRACT FROM PUBLISHER]

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs. [ABSTRACT FROM AUTHOR]

paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. This paper adopts two multimedia/DSP design examples, i.e., a multitransform design for H.264 and a versatile multimedia functional unit (VMFU), to evaluate the proposed SPST. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other. The multitransform design can compute three transforms which are required in 11.264 encoding while the VMFU possesses six com- monly used multimedia/DSP functions, namely, addition, subtraction, multiplication, MAC, interpolation, and sum-of-absolute-difference. After optimizing the design elaborately, we find that the proposed SPST can, respectively, save 27% and 24% power dissipation on average of the H.264 multitransform design and the VMFU at the expense of less than 20% area augmentation. [ABSTRACT FROM AUTHOR]

Dynamic element matching (DEM) is widely used in multibit digital-analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performance-enabling technique in delta-sigma data converters which require low-resolution but high-linearity DACs. More recently, segmented DEM architectures have made high-resolution Nyquist-rate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. [ABSTRACT FROM AUTHOR]

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-μm CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10-12 when the input pseudo-random bit sequence (PRBS) data pattern has a pattern length of 215 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (UIpp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231 - 1. [ABSTRACT FROM AUTHOR]

This paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering the threshold voltage of its devices. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst case coupling capacitance. Two implementations of this bus architecture are proposed, the alternate-Vt and the alternate forward body biased schemes, and are compared to a conventional bus scheme. For a flop distance of 1800 μm, the proposed schemes use the gained delay slack to reduce the total device width, and thus reducing the energy dissipation by 31.2%. For a 500-ps cycle time, the proposed bus schemes increase the maximum distance between flip-flops by 33%. [ABSTRACT FROM AUTHOR]

This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing. This is in sharp contrast with the steady-state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay, and the percentage of maximum undershoot when the circuit exhibits an underdamped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product. The experimental results carried out by RSPICE simulation verify the accuracy of our models. [ABSTRACT FROM AUTHOR]

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations. [ABSTRACT FROM PUBLISHER]

This paper presents the derivation of the most energy-efficient source functions by using calculus of variations. The fundamental theorem of calculus of variations for finding the functions that are local minima or local maxima of the integral is first explained. The theorem is then applied to derive analytically the source functions that minimize energy dissipation in circuits during transient. In particular, the most energy-efficient input current function and voltage source function for charging series R-C circuit are derived and proved to be a constant function and a raised ramp function respectively. The theorem of calculus of variations is extended for other common first order linear circuits as well. Their most energy-efficient source functions and lowest energy dissipation expressions are summarized in compact parameters involving speed and energy trade off limits. Numerical results are illustrated to depict the upper limit of speed-energy trade off and to justify the consistency with the analytical results. Application of the most energy-efficient source function for charging and discharging the capacitor of supercapacitor and adiabatic circuits is discussed along with comparison with other functions. [ABSTRACT FROM AUTHOR]

Energy storage technology is becoming more and more important in today's environmentally conscious society. In the conventional method of directly charging a capacitor under a constant power supply voltage, the amount of energy dissipation is the same as the energy stored in the capacitor. In this paper, we propose the stepwise charging of a capacitor by consecutively changing the duty ratio of the DC-DC down converter. In N step charging, the energy dissipation is reduced to one Nth when compared with the conventional direct charging. The reduction of the dissipated energy is verified by SPICE simulations and by breadboard experiments, through which an energy reduction of one fourth and one eighth is confirmed from the measured power supply currents in four and eight step charging, respectively. [ABSTRACT FROM PUBLISHER]

This paper introduces a reordered overlapped search mechanism for high-throughput low-energy content-addressable memories (CAMs). Most mismatches can be found by searching a few bits of a search word. To lower power dissipation, a word circuit is often divided into two sections that are sequentially searched or even pipelined. Because of this process, most of match lines in the second section are unused. Since searching the last few bits is very fast compared to searching the rest of the bits, we propose to increase throughput by asynchronously initiating second-stage searches on the unused match lines as soon as a first-stage search is complete. In our circuit implementation, each word circuit is independently controlled by a locally generated timing signal rather than a global signal. This allows the circuits to be in the required phase for their own local operation: evaluate or precharge, instead of having to synchronize their phase to the rest of the word circuits, which greatly reduces the cycle time. As a design example, a 128\,\times\,64-bit CAM is implemented and evaluated by HSPICE simulation under a 90 nm CMOS technology. The proposed asynchronous CAM operates 5.98 times faster than a synchronous CAM with 14.2% smaller energy dissipation. The post-layout proposed CAM achieves 385-ps cycle delay time and 0.773 fJ/bit/search and is also evaluated under different corner conditions and PVT variations to guarantee it operates properly. [ABSTRACT FROM PUBLISHER]

A false key-based advanced encryption standard (AES) technique is proposed to prevent the stored secret key leaking from the substitution-box under correlation power analysis (CPA) attacks without significant power and area overhead. Wave dynamic differential logic (WDDL)-based XOR gates are utilized during the reconstruction stage to hide the intermediate data that may be highly correlated with the false key. After applying the false key and designing the reconstruction stage with the WDDL, the minimum measurement-to-disclose value for the proposed lightweight masked AES engine implementation becomes over 150 million against CPA attacks. As compared to an unprotected AES engine, the power, area, and performance overhead of the proposed AES implementation is negligible. [ABSTRACT FROM AUTHOR]

Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication. Two multi-modulus multipliers that reuse the hardware resources amongst the modulo 2^n-1, modulo 2^n and modulo 2^n+1 multipliers by virtue of their analogous number theoretic properties are proposed. The former employs the radix-2^2 Booth encoding algorithm and the latter employs the radix-2^3 Booth encoding algorithm. In the proposed radix-2^2 and radix-2^3 Booth encoded multi-modulus multipliers, the modulo-reduced products for the moduli 2^n-1, 2^n and 2^n+1 are computed successively. With the basis of the radix-2^2 Booth encoded modulo 2^n+1 and radix-2^3 Booth encoded modulo 2^n-1 and modulo 2^n+1 multiplier architectures, new Booth encoded modulo 2^n multipliers are proposed to maximally share the hardware resources in the multi-modulus architectures. Our experimental results on \2^n-1,2^n,2^n+1\ based RNS multiplication show that the proposed radix-2^2 and radix-2^3 Booth encoded multi-modulus multipliers save nearly 60% of area over the corresponding single-modulus multipliers. The proposed radix-2^2 and radix-2^3 Booth encoded multi-modulus multipliers increase the delay of the corresponding single-modulus multipliers by 18% and 13%, respectively in the worst case. Compared to the single-modulus multipliers, the proposed multi-modulus multipliers incur a minor power dissipation penalty of 5%. [ABSTRACT FROM PUBLISHER]

This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their operating frequencies. To verify the operation principles, the VCO and DCO are both fabricated in 90 nm CMOS technology. The tuning range of VCO is from 52.2 GHz to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. It dissipates 8.7 mW from a 0.7-V supply, and the chip size is 0.28\times 0.36\ mm^2. On the other hand, the DCO is capable of covering frequency range from 37.6 GHz to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5\times 0.15\ mm^2. [ABSTRACT FROM AUTHOR]

This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at Eb/No of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder. [ABSTRACT FROM PUBLISHER]

The total harmonic distortion (THD) and the power supply noise, qualified by the power supply rejection ratio (PSRR) and by the power supply induced intermodulation distortion (PS- IMD), are recognized to be potential drawbacks of class D am- plifiers. In this paper, analytical expressions for the THD, PSRR, and PS-IMD of the bang-bang control class D amplifier (bang-bang amp) are derived; the bang-bang amp is arguably the most power- efficient class D amp for low-voltage power-critical applications in- cluding hearing aids. Based on the derived expressions, the effects of important parameters on the THD, PSRR, and PS-IMD are in- vestigated, providing good insight to the design of the bang-bang amp to meet given design specifications. The analytical analyses are verified by comparing them against HSPICE simulations and hardware measurements. The bang-bang amp is also compared against the prevalent pulsewidth modulation class D amp, and in most cases, the former is shown to possess superior parameters, including lower power dissipation and hardware advantages for low-voltage power-critical applications. [ABSTRACT FROM AUTHOR]

In this paper, we consider the robust filtering problem for discrete time-varying systems with delayed sensor measurement subject to norm-bounded parameter uncertainties. The delayed sensor measurement is assumed to be a linear function of a stochastic variable that satisfies the Bernoulli random binary distribution law. An upper bound for the actual covariance of the uncertain stochastic parameter system is derived and used for estimation variance constraints. Such an upper bound is then minimized over the filter parameters for all stochastic sensor, delays and admissible deterministic uncertainties. It is shown that the desired filter can be obtained in terms of solutions to two discrete Riccati difference equations of a form suitable for recursive computation in online applications. An illustrative example is presented to show the applicability of the proposed method. [ABSTRACT FROM AUTHOR]

We propose an energy barrier model of Static Random Access Memory (SRAM). The model provides useful insights about memory error rates for write, read, and retention. We introduce the concept of intrinsic energy margin induced write failure. The proposed model is employed for evaluating various write and read assist mechanisms and their potential in modulating the memory failures. Our analysis reveals that this model is very effective in predicting the behavior of SRAM stability and can be used as a tool to expedite the early phases of design to build assist circuits. Additionally, it can also be used to optimize energy dissipation of SRAM cache. [ABSTRACT FROM AUTHOR]

A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite impulse response filters for a post-LPDDR4 interface in a 65-nm CMOS technology is proposed. The proposed cascaded-equalizer removes the received long-tail inter symbol interference with the help of an IIR filter while the coefficients for the cascaded-equalizer are adaptively calibrated. In addition, the received single-ended ground-terminated data are converted to the differential pair by the proposed input buffer using a calibrated reference voltage. In the transmitter (TX), an output driver with controllable active inductors is proposed to reduce both power consumption and design complexity. At the maximum operating data rate, the measured power efficiencies of TX and receiver are 1.16 and 3.02 pJ/b, respectively, excluding the power dissipation of internal phase locked loop. In addition, the overall active area is 0.0091 mm2. [ABSTRACT FROM PUBLISHER]

Ternary content-addressable memory (TCAM) is a popular hardware device for fast routing lookup and an attractive solution for applications such as packet forwarding and classification. However, the high cost and power consumption are limiting its popularity and versatility. In this paper, a low leakage power TCAM architecture which uses two-side self power gating technique is proposed to reduce the leakage power dissipation of the mask SRAM cells. The TCAM mask cells are divided into several segments, and the mask bits of one segment are the same except for the boundary segment. In this design, the boundary segment is activated and the others are disabled so that the leakage power can be reduced. The experimental results show that average 26% leakage power can be reduced by using UMC 90 nm CMOS process with 1.0 V supply voltage when compared with the traditional TCAM architecture. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm^2 QRD chip, fabricated in 0.13 \mum 1P8M CMOS technology, demonstrate that the proposed design for 4\,\times\,4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25^\circC. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency. [ABSTRACT FROM AUTHOR]

Dissipativity is an important property of individual systems that guarantees a stable interconnected system. However, due to errors in the modeling process weakly non-dissipative models may be constructed. This paper introduces an enhanced method to perturb a non-dissipative LTI system in order to enforce dissipativity using spectral perturbation results for para-Hermitian pencils. Compared to earlier algorithms the new method is applicable to a wider class of problems, it utilizes a simpler framework, and employs a larger class of allowable perturbations resulting in smaller perturbations. Moreover, system stability can be enforced as well. Numerical examples are provided to show the effectiveness of the new approach. [ABSTRACT FROM AUTHOR]

This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-\mum CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 \muW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a new stage-sharing technique in a discrete-time (DT) 2–2 MASH delta-sigma (\Delta \Sigma) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2–2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13∼\mum CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power. [ABSTRACT FROM AUTHOR]

This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-\mu\ m CMOS technology are presented. [ABSTRACT FROM PUBLISHER]

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 ÷ 40% energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient low-complexity pulse-generator design technique for multiband impulse-radio ultrawide-band (IR-UWB) system in 0.18-μm CMOS technology. The short pulses are generated based on the on/off switching operation of an oscillator with subband switching functionality, which is mandatory for multiband IR-UWB systems. The relation between the oscillator switching operation and the resulting output pulse envelope, which determines pulse spectral characteristics, is analyzed, and the design guidelines for topology and component values are presented. Measurements show the output pulses with the duration of 3.5 ns, which corresponds to 520-MHz bandwidth. The output pulse spectrum centered at 3.8 GHz fully complies with the Federal Communication Commission spectral mask with more than 25 dB of sidelobe suppression without the need for additional filtering. Thus, the low-complexity pulse generator can maintain its simplicity for low cost with core chip size of 0.3 mm². The pulse generator shows an excellent energy efficiency with average energy dissipation of 16.8 pJ per pulse from 1.5-V supply. The proposed pulse generator is best suited for energy-detection IR-UWB systems. [ABSTRACT FROM AUTHOR]

Hardware search engine (HSE) plays a major role to speed up the search operation in wireless applications. Ternary content addressable memory (TCAM) is such an engine which performs the search in a single clock cycle but the use of separate content and mask storage, various wordlines for read/mask/write, and decoupled data/search lines require substantial design area and consume relatively high power. This article proposes implementation of a state of the art energy-efficient quasi-static ternary fully associative cache tag for wire speed memory access. A 4-T static content and dynamic mask storage have been used with coupled data and search line for reducing the energy dissipation during search. The proposed 128 $\times$ 32-bit TCAM tag with selective matchline evaluation scheme has been implemented with predictive 45-nm CMOS process and simulated in SPECTRE at the supply voltage of 1.0 V. The design dissipates an energy of 1.72-fJ/bit/search with a reduction of 32% in the cell area compared to the traditional TCAM. [ABSTRACT FROM PUBLISHER]

We propose a general model for array-based approximate arithmetic computing (AAAC) to guide the minimization of processing error. As part of this model, the Error Compensation Unit (ECU) is identified as a key building block for a wide range of AAAC circuits. We develop theoretical analysis geared towards addressing two critical design problems of the ECU, namely, determination of optimal error compensation values and identification of the optimal error compensation scheme. We demonstrate how this general AAAC model can be leveraged to derive practical design insights that lead to optimal tradeoffs between accuracy, energy dissipation and area overhead. To further minimize energy consumption, delay and area of AAAC circuits, we perform ECU design simplification by introducing logic don't cares. By applying this model and using a commercial 90 nm CMOS standard cell library, we propose an approximate 16 \times 16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less energy and area compared with theoretically the most accurate fixed-width Booth multiplier. Furthermore, it reduces average error, max error and mean squared error by 11.11%, 28.11%, and 25.00%, respectively, when compared with the most accurate reported approximate Booth multiplier and outperforms the same design significantly by 19.10% for the energy-delay-mean squared error product. Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit. To further reduce error and cost by utilizing extra signatures and don't cares, we demonstrate a 16-bit fixed-width squarer that improves the energy-delay-max error product by 15.81%. [ABSTRACT FROM AUTHOR]

A mechanism for the reduction of dynamic energy dissipation based on energy recovery resonant switching in a computing circuit is described. The resonant circuit with controlled switches conserves energy by recovering 90% of energy that would be otherwise lost during logic state transitions. The new approach of incorporating an energy recovery storage capacitor in the resonant circuit helps to initialize the logic operation and moves the energy back and forth to the load capacitance. This energy-conserving approach preserves thermodynamic entropy, ideally preventing heat generation in the system. This proposed method is used for generating an energy-efficient “flat-topped” (quasi-trapezoidal) waveform, which is required to perform the low power digital logic computation, especially for clocking in the system applications. [ABSTRACT FROM AUTHOR]

A 0.18-\mum CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10^-12 BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-\mum standard CMOS technology with 0.3\,\times\,0.8-mm^2 active area. [ABSTRACT FROM AUTHOR]

Energy loss due to top/bottom plate parasitic capacitances is one of the factors determining the efficiency of integrated switched capacitor DC/DC converters. This loss is particularly significant when MOS gate or deep trench capacitors are used. We propose a technique for top/bottom-plate charge recycling that can be applied with low overhead independently of the converter architecture. Two examples of application of the technique are presented. First, it is shown how the technique can be applied to any converter by transforming it to an interleaved implementation. This approach is demonstrated in a series-parallel 1/3 down converter achieving a maximum load power of 240 \mu\textW. Simulation results show an improvement of 7% in the efficiency by decreasing the top/bottom-plate parasitic capacitance losses by 52%. The second example considers an architecture where the proposed technique can be directly applied without additional transformations of the converter implementation. It is a ring modular architecture converter, which was fabricated in a 130 nm CMOS process. An efficiency improvement of up to 4% was achieved in measurements by reducing the top/bottom plate losses by 70%, thus reaching an outstanding efficiency of 80.6% at a conversion ratio of 2/3 and a maximum load power of 2.2 mW. [ABSTRACT FROM AUTHOR]

Power analysis attacks utilize the correlation between the dissipated power and the processed data. Although the instantaneous power dissipation contains information it cannot be exploited without full reverse engineering. This article explores data-dependent instantaneous (intra-cycle) power dissipation and shows that it can be used as additional source of randomness that can be utilized as a barrier against power analysis attacks. Noiseless circuit simulations conducted on 65 nm standard CMOS and standard-cell-based dual-rail SBOXs show that large data-dependent variance in propagation delays enhance the immunity of the circuits. [ABSTRACT FROM PUBLISHER]

An ultra-low-power wake-up receiver is proposed to reduce the energy consumption through adoption of two wake-up modes of operation with different power dissipations and detection bandwidths. During the Monitoring (MO) mode, the start frame bits are received at a data rate of 10 kbps, while during the Identifier (ID) mode the remaining wake-up pattern is transmitted at 200 kbps. By lowering the gain of the front-end amplifier in the MO mode the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver. The proposed wake-up receiver is designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm^2 for the target frequency range of 902–928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 \muW and 22.9 \muW during MO and ID modes, respectively. [ABSTRACT FROM AUTHOR]

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the subthreshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near-VT and sub-VT operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near-VT voltage for robust read. Energy characterization is performed at nominal, near-VT, and sub-VT supply voltages. The minimum energy point is reached for near-VT read operation with a total read+write energy of 735 fJ. [ABSTRACT FROM PUBLISHER]

A high-performance buffer amplifier topology for liquid crystal display drivers is presented. The proposed amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself, without additional power dissipation. Experimental results demonstrate that the suggested buffer can drive a 1000-pF capacitive load with a 5.7\-V/\mus slew-rate and a 0.71\-\mus settling time, while drawing 32\-\muA overall quiescent current from a 5-V power supply. [ABSTRACT FROM PUBLISHER]

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after calibration. The converter offers 3.8 effective number of bits (ENOB) at 1.6 GS/s sampling rate with a low frequency input signal and more than 1.8 GHz effective resolution bandwidth (ERBW) at this sampling rate. The converter consumes mere 15.5 mW from a 1.8 V supply, yielding an FoM of 695 fJ/conversion.step and occupies 0.3 mm^2 in a 0.18 \mum standard CMOS process. [ABSTRACT FROM PUBLISHER]

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3\,\times\,3 kernel. The proof-of-concept circuit is implemented in 0.35 \mum CMOS technology, and contains a 64\,\times\,64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 \muW per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s. [ABSTRACT FROM AUTHOR]

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-μm SOl CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 Ω loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si. [ABSTRACT FROM AUTHOR]

A 330-MHz fifth-order Gm-C continuous-time low-pass filter with 24-dB boost is presented. Existing solutions are found to be unsuitable for low-power, wide-band, and high-boost operation. The proposed solution realizes two symmetric real axis zeros by efficiently combining transfer functions associated with all nodes of cascaded biquad cells. Application of Gilbert cell as a variable transconductor, for achieving constant parasitic capacitance across wide programmability range, is illustrated. A new common-mode feedback error amplifier that improves common-mode accuracy without compromising on bandwidth or circuit complexity is introduced. A prototype is fabricated in a standard 0.35-mum CMOS process. Experimental results show -41 dB of IM3 for 250-mV peak-peak swing with 43 mW of power dissipation [ABSTRACT FROM PUBLISHER]

Wordlength determination is an indispensable task in digital hardware implementations of signal processing algorithms because the wordlength affects power consumption and system performance. There is a tradeoff between power consumption and system performance when searching for the optimum wordlength. We have developed a technique of dynamically controlling the wordlength used in the signal processing algorithms of wireless orthogonal frequency-division multiplexing (OFDM) receivers. The receiver dynamically changes the wordlength on the basis of the conditions in the propagation environment while satisfying the user-required communication quality. That is, the system optimizes the wordlength while operating by sensing its own performance and gradually adjusting this wordlength to improve performance. Testing revealed that, for a packet error rate (PER) of 10[sup-2], the application of this technique to an OFDM receiver reduces energy dissipation by 18.1%-30.2%. [ABSTRACT FROM AUTHOR]