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In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

In this paper, a design methodology for SiGe HBT-based low-noise amplifiers (LNAs) is proposed that can be utilized for both sub-1-dB noise figure (NF) and wide bandwidth as an alternative to the conventional simultaneous input noise and power matching technique. This paper focuses on the removal of the series base inductor and the inclusion of an output matching network as a design parameter that can be used to achieve both sub-1dB NF and wide bandwidth. The effects of the mentioned design parameters on NF and bandwidth are described and analyzed, including the comparison of results with the conventional design technique. To demonstrate the validity of the analysis and impact of utilizing base-to-collector capacitance on LNA performance metrics, two different LNAs implemented in a 0.13- $\mu \text{m}$ SiGe technology. The first LNA achieves a lower than 1-dB NF with 26-dB gain at 8.5 GHz, and the second LNA exhibits wideband operation, with a better than 10-dB return losses in the range of 8–35 GHz and lower than 3-dB NF from 6 to 20 GHz. The sub-1-dB LNA reaches −17.3 dBm of input-referred compression point (IP1dB), with a power consumption of 62 mW and an area of 0.795 mm2. The wideband LNA achieves 17.6 dB of peak gain with a 48.5-mW power consumption and 0.69-mm2 chip area. To the best of our knowledge, this paper achieves the best NF performance in the literature utilizing a SiGe technology, while the wideband LNA exhibits the best operational bandwidth, together with a reasonable low-noise performance. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in $0.18 \mu \text{m}$ technology occupying the area of about $71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$ is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory. [ABSTRACT FROM AUTHOR]

The present manuscript relies on the companion paper entitled “Memristor Circuits: Flux–Charge Analysis Method,” which has introduced a comprehensive analysis method to study the nonlinear dynamics of memristor circuits in the flux–charge $(\varphi ,q)$ –domain. The Flux–Charge Analysis Method is based on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in terms of incremental fluxes and incremental charges. The straightforward application of the method has previously provided a full portrait of the nonlinear dynamics and bifurcations of the simplest memristor circuit composed by a capacitor and a flux-controlled memristor. This paper aims to show that the method is effective to analyze nonlinear dynamics and bifurcations in memristor circuits with more complex dynamics including Hopf bifurcations (originating persistent oscillations) and period–doubling cascades (leading to chaotic behavior). One key feature of the method is that it makes clear how initial conditions give rise to bifurcations for an otherwise fixed set of circuit parameters. To the best of the authors’ knowledge, these represent the first results that relate such bifurcations, which are referred to in the paper as Bifurcations without Parameters, with physical circuit variables as the initial conditions of dynamic circuit elements. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

This paper addresses the issue of the optimal design of a grounded fractional order inductor using a generalized impedance converter. The nonidealities of the op amps have been taken into account while formulating the approximate frequency characteristics of the fractional order inductor for both Type-I and Type-II realizations. Based on these formulations a set of design guidelines is proposed to achieve minimum phase and magnitude errors for the realized fractional inductor. The minimization conditions have been validated by several simulation and experimental results. [ABSTRACT FROM AUTHOR]

Impedance transformation is one of the central concepts in high-frequency circuits and systems and is used ubiquitously for optimal power matching, noise matching, and high-efficiency power delivery to the antenna by power amplifiers. The matching network can be generally expressed as a path on the Smith chart and given the load and source impedances, there are theoretically infinite ways to achieve the transformation. When losses are included, each path will encounter a different loss, and currently, no comprehensive theory exist for finding the most optimal matching network. Furthermore, the networks will also provide different bandwidths of operation. Due to the matching network losses, it is often not optimal to force conjugate matching for maximizing end-to-end power transfer efficiency. In this paper, we provide a method toward finding 1) the globally most efficient path between two arbitrary impedances with lossy passives; 2) given the source and the load impedances, the optimal (typically non-conjugate) impedance to match and the highest efficiency path to reach the impedance; and 3) upper bounds on achievable efficiencies under the various scenarios. This paper also proposes ways to combine this method with nonlinear load-pull simulations for optimal combiner and matching network for integrated power amplifiers. This analysis creates interesting ways to maximize efficiency and bandwidths simultaneously and the paper also discusses this joint optimization. To the best of our knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives. [ABSTRACT FROM PUBLISHER]

The paper considers a relevant class of networks containing memristors and (possibly) nonlinear capacitors and inductors. The goal is to unfold the nonlinear dynamics of these networks by highlighting some main features that are potentially useful for real-time signal processing and in-memory computing. In particular, an analytic treatment is provided for dynamic phenomena as the presence of invariant manifolds, the coexistence of different regimes, complex dynamics and attractors and the phenomenon of bifurcations without parameters, i.e., bifurcations due to changing the initial conditions of the state variables for a fixed set of circuit parameters. The paper also addresses the issue of how to design pulse independent voltage or current sources to steer the network dynamics through different manifolds and attractors. Two relevant examples are worked out in details, namely, a variant of Chua’s circuit with a memristor and a nonlinear capacitor and a relaxation oscillator with a memristor and a nonlinear inductor. In the latter example, the paper also studies the effect on manifolds and coexisting dynamics when real memristive devices are accounted for using a class of extended memristor models. The analysis is conducted by means of a recently developed technique named flux-charge analysis method (FCAM). Numerical simulations are presented to confirm the theoretic findings. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

This paper presents an area-efficient current-mode-logic (CML)-based divider, with a tunable self-resonant frequency for locking range (LR) extension. Specifically, a negative- $g_{m}$ (NG) cell is inserted between the resonated shunt-peaking inductor and the load resistor to shift the divider’s sensitivity curve (SC), enabling concurrently a higher operating frequency and a wider LR. We also use the injection-locking concept, together with a graphical phasor diagram with the frequency-phase information, to systematically explain the LR-extension mechanism. Prototyped in a 65-nm CMOS, the divider occupies a tiny active area of 0.0018 mm2. The measured LR is 153% (4–30 GHz) while consuming 4.06–4.28 mW at 30 GHz under a single 1.2-V supply. The performance corresponds to two figure of merits: FOM $_{\mathbf {Pdc}}$ of 25.5 dB and FOM $_{P}$ of 71.5, both compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

In this paper, a high-order nonlinear disturbance observer-based fractional-order sliding mode control (FOSMC) strategy is proposed for DC/DC buck converters in the presence of mismatched disturbances, ensuring the properties of both stability and dynamic performance. Traditional sliding mode control can deal with matched disturbances while achieving desired closed-loop performance, unfortunately it is particularly sensitive to mismatched disturbances. In the proposed control structure, two nonlinear disturbance observers are constructed to estimate both matched and mismatched disturbances in finite time. Then, the estimated variables are used for the fractional-order sliding mode surface design, where a super twisting sliding mode controller is designed to drive the states of the system to track their desired values. Comparing with the traditional SMC, the proposed method not only reduces the sensitivity of the system to mismatched disturbance, but also improves the transient performance of the system. Simulation and experimental results have comprehensively illustrated the feasibility and effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz. [ABSTRACT FROM PUBLISHER]

This paper considers a large class of memristor circuits of arbitrary order, and containing an arbitrary number of flux- or charge-controlled memristors, for which a state equation (SE) description can be obtained. By means of the SEs, it is shown that the state space of each circuit can be decomposed in infinitely many manifolds, and that in the autonomous case, each manifold is positively invariant and is characterized by a different reduced-order dynamics and attractors. These results are the basis for extending the analysis to the non-autonomous case, where time-varying independent sources are present. In particular, the chief result obtained in this paper shows how to analytically design external pulses for programming memristor circuits, i.e., how invariant manifolds and attractors can be changed and controlled by applying suitable charge or flux sources via time-varying voltage and/or current pulses with finite time duration. The main results are obtained by relying on a recently introduced technique for the analysis of memristor circuits in the flux-charge domain. [ABSTRACT FROM AUTHOR]

Three types of bifurcations (instabilities) in the DC-DC converter under valley current mode control (VCMC) are analyzed, which is an extension of a recent paper on the peak current mode control (PCMC). The three bifurcations are border-collision, period-doubling, and saddle-node bifurcations. The corresponding critical (instability) conditions are derived. The derived conditions divide the parameter space into different operating modes. Contrary to the general belief that the critical conditions for VCMC and PCMC are symmetric with respect to the duty cycle D=1/2, most critical conditions are actually asymmetric. The dynamics symmetry is converter, bifurcation, loading, and parameter dependent, verified by bifurcation diagrams and time-domain simulations. The VCMC boost converter has rich dynamics and it is extensively analyzed. [ABSTRACT FROM AUTHOR]

An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

This paper presents a novel analysis of nonlinear circuits useful for the computation of the reactive power from only terminal measurements. The method computes the reactive power of unknown circuits based on the physical understanding of Maxwell equations. The proposed method is able to identify instantaneous quantities (circuit parameters, powers, etc.) for two physical equivalent models: series and parallel circuits. The parallel equivalent model shows advantages for multi-subsystems. Several numerical examples are provided for validation of the proposed method and to illustrate step-by-step the calculation details. To be compatible with digital instrumentation, a time discrete formulation is used for all calculations. All examples are simulated in MATLAB and the EMTP (Electro-Magnetic Transients Program). [ABSTRACT FROM AUTHOR]

This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4–11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOMT and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only $0.1 \,\, \times 0.395\,\,\mu \text{m}^{{2}}$. [ABSTRACT FROM AUTHOR]

This paper proposes a family of integrated multiple output isolated dc–dc converters, in which switches are hybrid utilized. Compared with the conventional separate $N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness. [ABSTRACT FROM PUBLISHER]

In this paper, conditions for checking the realizability of fractional-order impedance functions by passive networks composed of a fractional element (either a fractional capacitor or a fractional inductor) and some RLC components are derived. To this end, at first the newly obtained conditions for realizability of fractional-order impedance functions by a passive network composed of a fractional capacitor and some RLC components are extended to include the case that the polynomials involving in the impedance function can have roots on the imaginary axis. Then, the necessary and sufficient conditions are found on a fractional-order impedance function to be realized by a passive network composed of a fractional element and some RLC components. Furthermore, a procedure for finding the realization in the realizable cases is proposed. Finally, the realizability conditions for a special class of fractional-order impedance functions are simplified. [ABSTRACT FROM AUTHOR]

In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments. [ABSTRACT FROM AUTHOR]

This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOM $_{\mathbf {T}}$ are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is $0.146\times 0.205$ mm $^{\mathbf {2}}$. [ABSTRACT FROM AUTHOR]

This paper revisits the behavioral modeling of inductors used for Switch-Mode Power Supply (SMPS) design. A novel unified behavioral modeling for power inductors is herein proposed, which considers the DC current passing through the device and the equivalent applied voltage and switching frequency as model inputs, and the resulting peak-to-peak current ripple, total power loss and temperature as model outputs. The proposed behavioral modeling relies on simple analytical formulas, discovered from experimental measurements by using a multi-objective evolutionary algorithm. The resulting behavioral models allow to define the “Constrained Operating Area” of a power inductor, which describes the boundary area in the three-dimensional domain of switching frequency, DC current and equivalent voltage that can be applied to the component while maintaining its peak-to-peak current ripple, power loss and temperature within given limits. The experimental case studies presented in the paper eventually confirm the reliability of the proposed behavioral modeling approach and of the resulting models, in the assessment of the suitability of a given inductor and in the comparative evaluation among different inductors for a given SMPS application. [ABSTRACT FROM AUTHOR]

This paper presents various techniques to achieve high efficiency for the bidirectional Cascaded-Buck-Boost converter. This converter has the features of low voltage across the switches and positive output voltage. The objective of this paper is to optimize the magnetics design to reduce the total losses in a low power non-isolated DC-DC circuit. A rigorous loss model with component nonlinearities is developed to determine the power loss distribution. It is validated by simulations and experiments. Based on the results of the power loss analysis and due to the low inductor profile and high efficiency target, nanocrystalline material will be the best candidate. Therefore, a new small volume low profile planar-nanocrystalline inductor is designed. Various deep de sign aspects for core and copper are discussed. The Finite-Element-Analysis (FEA) method is used to examine and visualize the inductor design. By implementing the planar-nanocrystalline inductor, a California Energy Commission (CEC) weighted efficiency of 99.05% for the buck mode and 98.98% for the boost mode are achieved with a peak efficiency of 99.24% and 99.21%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{\mathrm {out}}$) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{\mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{\mathrm {out}}$. A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{\mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $\mu {\mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained when excited by a 160-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]

In a capacitive wireless power transfer system, due to the pF-level coupling capacitance, resonant inductors are commonly used at the primary side to boost voltage and at secondary side to boost the current. However, the inductors are bulky, in particular when it comes to integration, thereby not preferred by some space-sensitive applications like smartphones, smart glasses and headphones. This paper proposes a capacitive wireless power transfer architecture with no inductors at the receiver side. A high conversion ratio step down switched capacitor converter (SCC-CPT), rather than inductors, is used to compensate for the impedance mismatch between the secondary side of the capacitive coupler and the load. The analysis method and its associated design procedure of the SCC-CPT system is developed with the target of clarifying the tradeoffs among the secondary side efficiency, coupler voltage stress, receiver side integrability, and the primary side compensation network gain. Finally, a 7.5 W, 12 MHz SCC-CPT prototype was constructed to validate the proposed analysis and design. The measured system efficiency is 75.6 % at 7.5 W output, and the secondary side switched capacitor converter efficiency is 96.4 %. [ABSTRACT FROM AUTHOR]

Present universal serial bus (USB) battery chargers often suffer from limitations to meet the increasing demand for quick charging due to compromised power efficiency and complicated hardware implementation. In this paper, we propose a charge unifiable (QU) control scheme that enables a battery charger to improve power efficiency in a low-profile hardware manner. This scheme features fully soft-switching (vis-à-vis hard switching) and single control scheme (vis-à-vis multiple) for distinct constant current (CC) and constant voltage (CV) charging modes. To the best of authors’ knowledge, the proposed QU control scheme is the first to simultaneously offer fully soft-switching, innate CC-and-CV regulation, and seamless CC-to-CV transition. To verify the proposed design, we monolithically realize a low-profile high-efficiency fast battery charger based on this scheme. The prototype embodying a tiny 470-nH output inductor supports a maximum input voltage of 16V, output voltage of 2.2-4.2 V, output current of 0.1-2 A, and peak power efficiency of 96.2%. When benchmarked against state-of-the-art counterparts, the proposed charger features at least $2.1\times $ smaller inductor and 7.2% higher power efficiency at both the maximum and the minimum output power charging scenarios. Further, this charger is the only design that features ≥91% power efficiency in the whole load range. [ABSTRACT FROM AUTHOR]

This paper investigates the simplified realization problem of a special class of positive-real admittances similar to biquadratic functions but with an extra pole at the origin, which is widely used in the analysis of suspension systems. The results in this paper are motivated by passive mechanical control with the inerter. The concept of strictly lower complexity is first defined, whose indices in this paper are the total number of elements, the number of resistors (dampers), and the number of capacitors (inerters). We then derive a necessary and sufficient condition for this class of admittance to be realized by the networks that are of strictly lower complexity than the canonical realization by the Foster Preamble method. To solve this problem, it is shown that it suffices to consider the following: 1) networks with at most four elements, 2) irreducible five-element resistor-inductor (RL) networks, and 3) irreducible five-element resisitor-inductor-capacitor (RLC) networks. Other cases are shown to be impossible. By finding their corresponding network configurations through a series of constraints and deriving the corresponding realizability conditions, the final condition can be obtained. Finally, the U-V plane and numerical examples are provided to illustrate the theoretical results. [ABSTRACT FROM PUBLISHER]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]

This paper introduces new fundamentals of the three-dimensional \nabla\times n RLC circuit network in the fractional-order domain. First, we derive the general formula of the typical equivalent impedance of the circuit network in different cases by using matrix transform method and the difference equation model. Then, we systematically investigate the effects of the five system parameters (inductance (L), capacitance (C), the number of circuit units (n), and fractional orders \alpha and \beta) on the impendence characteristics and the phase characteristics of two different cases. Specifically, interesting phenomena and laws are presented by the numerical simulations. Moreover, a comparative analysis about the impendence characteristics and the phase characteristics of the two cases for the fractional-order three-dimensional circuit network is studied in detail. Finally, the results of PSpice simulation are presented to validate the study. [ABSTRACT FROM AUTHOR]

A novel harmonic Class-C CMOS VCO architecture with improved phase noise performance and power efficiency is presented in this paper. The VCO is based on the widely adopted topology consisting in a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The Class-C operation mode is obtained through a low frequency feedback loop constituted by an operational transconductance amplifier operating the difference between the inductor center tap voltage and a reference voltage, pushing gate polarization voltage of VCO crossed pair devices well below their threshold voltage. The Class-C VCO achieves a theoretical 2.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator for the same current consumption. A prototype of the VCO is implemented in a standard RF 55 nm CMOS technology and compared to both a standard and an optimized VCO implemented in the same technology. All these VCOs share a copy of a unique resonator. The Class-C VCO is tunable over the frequency band 6.5–7.8 GHz and displaying an average phase noise lower than -127 dBc/Hz @ 1 MHz offset with a power consumption of 18 mW, for a state-of-the-art figure-of-merit of -187 dBc/Hz @ 1 MHz and -191 dBc/Hz @ 10 MHz offsets, respectively. [ABSTRACT FROM AUTHOR]

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of −115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of −181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J−1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., $Z(f_{0})=R_{\mathrm{ opt}}+jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=-j({3}\pi /{8})R_{\mathrm{ opt}}$), whereas the second MN realizes the optimal impedances of class-J−1 PAs (i.e., $Z(f_{0})=R_{\mathrm{ opt}}-jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=j({3}\pi /{8})R_{\mathrm{ opt}}$). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of $R_{\mathrm{ opt}}$. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two proof-of-concept class-J and class-J−1 PAs are designed and implemented in a 0.25- $\mu \text{m}$ GaAs process, where the proposed OMNs are employed in the designed circuits. The manufactured PAs show ≥28 dBm output power, ≥65% drain efficiency, and ≥61% power-added efficiency at 2 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an efficient hybrid energy harvesting interface to synergistically scavenge power from electromagnetic (EM) and piezoelectric (PE) sources, and drive a single load. The EM harvester output is rectified through a self-powered active doubler structure, and stored on a storage capacitor. The stored energy is then transferred to the PE harvester to increase the damping force and charge extraction. The total synergistically extracted power from both harvesters is more than the power obtained from each independently. The hybrid operation is validated through a compact and wearable platform that includes custom designed EM and PE harvesters for scavenging energy from human motion. The system supplies 1–3.4 V output for powering up wireless sensor nodes with a wide range of vibration frequency, and generates between 1– $100~\mu \text{W}$ at 90% maximum power conversion efficiency. The solution has superior power generation performance compared to previous stand-alone systems in the literature. [ABSTRACT FROM AUTHOR]

This paper proposes a new modeling approach for ferrite-core (FC) power inductors used in switch-mode power supplies (SMPSs). In particular, a novel power-loss-dependent inductance behavioral model is proposed, whose parameters can be identified through a limited set of proper experimental measurements of inductor current and voltage. Unlike conventional thermal modeling approaches, which require information on core temperature, the proposed behavioral model relies only on easily measurable quantities. The model is also suitable for being implemented in circuit simulators. By comparing PSIM simulations and experimental measurements on a buck converter for commercial FC inductors, we show that the model allows a reliable prediction of the steady-state inductor current, under different SMPS working conditions. [ABSTRACT FROM AUTHOR]

This paper presents an efficiency-enhanced low-profile zero-voltage-transition (ZVT) synchronous non-inverting buck-boost converter for 48-V tens-of-Watt output applications. By only using three auxiliary components shared between two switching nodes, zero-voltage switching (ZVS) of all four power switches and zero-current switching of the auxiliary switch are achieved in the proposed converter to minimize the switching power loss. Compared with the existing ZVT topologies, the proposed converter reduces the required number of auxiliary components, thereby decreasing the converter volume and power loss. In addition, the proposed converter can be configured into the buck mode with full ZVS capability to support a wide input range from 36 V to 90 V. Experimental results show that the proposed converter can operate at 1 MHz and deliver a maximum output power of 75 W. The measured peak power efficiencies achieve 92.5% and 96.3% in the buck-boost mode and buck mode, respectively. Compared with the state-of-the-art ZVS-based buck-boost counterpart, the proposed converter reduces the volume of the auxiliary circuit by ~2 times even with 28% increase in the maximum load current and two times reduction in the switching frequency, and provides higher peak power efficiencies in both buck-boost and buck modes. [ABSTRACT FROM AUTHOR]

A wide-input-range (5–115 V) current-accuracy-enhanced dc–dc LED driver is presented in this paper. A feedforward synchronous current control (FSCC) scheme is developed to improve the LED current accuracy over wide ranges of input and output voltages. In the FSCC, a reconfigurable valley current sensor is proposed to provide accurate positive and negative valley inductor current information for the controller corresponding to hard- and soft-switching modes, respectively. A dynamic peak reference generator is developed to automatically adjust the peak current reference value dependent on input and output voltages for reducing the deviations of the average LED current under different input voltages and numbers of output LED, thereby improving the current accuracy. Implemented in a 0.5- $\mu \text{m}$ 120-V CMOS process, the experimental results show that the proposed LED driver IC achieves a current accuracy within ±6.0% of the average LED current of 350 mA over an input voltage range from 5 to 115 V and numbers of series-connected LEDs from 1 to 25 by using only a small inductor of 10 $\mu \text{H}$. Compared with the state-of-the-art synchronous current control scheme, the variations of the LED current can be reduced by 2.3 and 4.2 times in the hard- and soft-switching modes, respectively, with the proposed LED driver using the FSCC. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconductor of the VCO is reduced by introducing a negative source impedance. A prototype VCO based on this topology is demonstrated in a 65 nm digital CMOS process. The VCO is operated from 23.9 to 26.9 GHz at a low supply voltage of 0.6 V, while achieving an ultra-low 1/ $f^{3}$ phase noise corner from 170 to 240 kHz across the tuning range. The phase noise is −110 dBc/Hz at 1 MHz frequency offset. The power consumption is 4.8 mW. The measurement results demonstrate that the VCO achieves a state-of-the-art phase noise performance in both the 1/ $f^{2}$ region and the 1/ $f^{3}$ region. [ABSTRACT FROM AUTHOR]

A high-voltage (HV) lithium-ion battery charger control chip with sharp mode transition and partial current control technique is proposed in this paper. The proposed sharp mode transition eliminates the transition region between constant current (CC) and constant voltage (CV) stages in traditional CC–CV chargers. This technique reduces the charging time and simplifies the compensator design. Furthermore, by adopting the HV partial current control technique, the charging current at the CC stage can be regulated only by sensing part of inductor current. The charger is designed and fabricated using Taiwan Semiconductor Manufacturing Company 0.25- $\mu \text{m}$ 1P3M bipolar-CMOS-DMOS HV process. With a 25-V input voltage, the output voltage (i.e., battery voltage) may range from 6 to 22 V and the maximum charging current is 2.5 A. The peak efficiency reaches 97%, occurring at 1-A charging current. [ABSTRACT FROM AUTHOR]

In this paper, based on fractional calculus, the fractional-order memristor, an arbitrary-order fracmemristor, is proposed to be implemented in the form of a lattice scaling analog circuit. Since the concept of the memristor is generalized from the classic integer-order memristor to that of the fractional-order memristor, fracmemristor, it is natural to ponder a challenging theoretical problem to propose a circuit theoretic methodology to achieve an arbitrary-order memristor by using the ordinary memristor and capacitor or inductor in the form of an analog circuit. Motivated by this need, in this paper, we propose an interesting analog circuit implementation method of an arbitrary-order memristor. The first step is the proposal for a novel feasible analog circuit implementation of an arbitrary-order lattice scaling fracmemristor. In particular, the hardware achievement of this arbitrary-order lattice scaling fracmemristor is mathematically derived and analyzed in detail. Second, the approximation performance, electrical characteristics, especially fingerprints, and analog circuit achievement of an arbitrary-order fracmemristor are experimentally analyzed in detail, respectively. The main contribution of this paper is the first proposal for the preliminary attempt of a feasible hardware achievement of an arbitrary-order fracmemristor and for the recognition of the fingerprints of fracmemristor. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz $0.3~\rm V_{pp}$ sinusoidal signals with 4 mV average output error at $100~\Omega $ load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at $1.2~\rm V_{dd}$. To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an RF energy harvesting and power management unit that operates across a wide range of available input power, from −24 to +15dBm. The system comprises an adaptive impedance matching network, a single-stage cross-coupled differential-drive rectifier, a start-up charge pump, an adaptive buck-boost converter, a maximum power point tracking (MPPT) circuit and a control loop to regulate the load voltage. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, guaranteeing that the power is being harvested at maximum efficiency. To boost the rectifier output, to accumulate energy in the storage capacitor and to provide energy to the load, a single-inductor buck-boost converter that has two inputs and three outputs is used. Circuit techniques that reduce the power consumption of the control circuits and that allow for adapting the interfaces between the antenna, the rectifier and the load are presented. The peak harvesting efficiency of the system is 40.2%, when presented with an RF source of -9.1dBm available power and 403.5MHz frequency. [ABSTRACT FROM AUTHOR]

The effects of resonator topology on the phase noise of LC oscillators are studied in this paper. It is shown that there is a neglected factor that can considerably influence the phase noise behavior of the oscillator. We designate this factor as the Inductance Energy Factor (IEF), which directly depends on the topology of the resonator. It is shown that through proper design of the resonator for a better IEF, the oscillator phase noise can be improved. It is also shown that by modifying the resonator structure to improve IEF, the phase noise does not have to be constrained by the minimum realizable inductance and its maximum quality factor. Therefore, the power-phase noise trade-off remains effective beyond this point. In the following, a general method to design the resonator circuit by a so-called evolutionary modification of the conventional LC tank is given. Illustrated simulations further help to confirm that phase noise improvements of more than 10 dB can be readily achieved by judicious design of the resonator circuit. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]