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In this paper, a novel saturation-based control method is proposed for high-order sliding mode (HOSM) dynamics with upper-triangular nonlinearities. Firstly, a new HOSM dynamics with upper-triangular nonlinearities is constructed based on the traditional HOSM dynamics, so as to reduce the uncertainties in the control input channel. Then, a HOSM controller is established by means of the adding a power integrator method such that the new HOSM dynamics is locally stabilized. Finally, the saturation-based controller is constructed by a combination of the saturation technique and the local HOSM controller to guarantee that the sliding variables can converge into a domain of attraction in a finite time and retain inside it thereafter. The rigorous stability analysis is made by the Lyapunov theory. A simulation example is also given to demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a family of algorithms based on sparse decompositions that detect anomalies in video sequences obtained from slow moving cameras. These algorithms start by computing the union of subspaces that best represents all the frames from a reference (anomaly free) video as a low-rank projection plus a sparse residue. Then, they perform a low-rank representation of a target (possibly anomalous) video by taking advantage of both the union of subspaces and the sparse residue computed from the reference video. Such algorithms provide good detection results while at the same time obviating the need for previous video synchronization. However, this is obtained at the cost of a large computational complexity, which hinders their applicability. Another contribution of this paper approaches this problem by using intrinsic properties of the obtained data representation in order to restrict the search space to the most relevant subspaces, providing computational complexity gains of up to two orders of magnitude. The developed algorithms are shown to cope well with videos acquired in challenging scenarios, as verified by the analysis of 59 videos from the VDAO database that comprises videos with abandoned objects in a cluttered industrial scenario. [ABSTRACT FROM AUTHOR]

In this paper, we consider the identification problem for nonlinear state-space models with skewed measurement noises. The generalized hyperbolic skew Student’s t (GHSkewt) distribution is employed to describe the skewed noises and formulate the hierarchical model of the considered system. A unified framework for estimating unknown states and model parameters is presented based on expectation-maximization (EM) algorithm, in which the forward filtering backward simulation with rejection sampling (RS-FFBSi) is employed to efficiently estimate the smoothing densities of the hidden states, and optimization method is adopted to update model parameters. One numerical study and the electro-mechanical positioning system (EMPS) are employed to verify the effectiveness of the developed approach. [ABSTRACT FROM AUTHOR]

In this paper, the problem of formation control is studied for second-order multi-agent systems with practical issues like mismatched uncertainties and obstacle avoidance. A reference correction algorithm based sliding mode control scheme is proposed to ensure the boundedness of each agent’s position tracking error. Both disturbance observer and artificial potential field are implemented to first tackle the problem of obstacle avoidance with the existence of mismatched uncertainties. The unreachable reference scenarios are then defined to describe the passive correcting behaviours of the multi-agent system when agents are trying to avoid obstacles. A distributed reference correction algorithm is developed for each agent to attenuate the harmful effects of passive correcting behaviours. The effectiveness of obstacle avoidance and boundedness of position tracking error are both verified by Lyapunov stability theory. Finally, multi-robot system based numerical simulations and comparisons are conducted to demonstrate the effectiveness of the proposed algorithm and controller. [ABSTRACT FROM AUTHOR]

In this paper, three Lorentzian based robust adaptive algorithms are proposed for identifying systems in presence of impulsive noise. The first algorithm called Lorentzian adaptive filtering (LAF) is derived from a sliding window type cost function with Lorentzian norm of past errors to combat adverse effect of impulsive noise on systems. The first and second order convergence analyses of the LAF algorithm are carried out in this paper. Then, to identify sparse systems in impulsive noise environment, l0 norm penalty is introduced to the cost function of the LAF algorithm leading to a new algorithm called Lorentzian hard thresholding adaptive filtering (LHTAF) which employs hard thresholding operator with a fixed hard thresholding parameter to obtain sparse solutions. The effect of the hard thresholding operator is further analyzed, and the analysis shows that a variable hard thresholding parameter offers significant improvement in the performance of the algorithm, and this result in the final algorithm called Lorentzian variable hard thresholding adaptive filtering (LVHTAF) where the hard thresholding parameter is adjusted adaptively. Simulation results show that the LVTHAF outperforms the existing robust sparse adaptive algorithms by producing lesser steady state mean square error. [ABSTRACT FROM AUTHOR]

This paper investigates the issue of global robust ${H_\infty }$ pinning synchronization for a class of complex networks with sampled-data-based event-triggered communication via a pinning control approach. The complex network is subject to network-induced time-varying delays, parametric uncertainties and external disturbances. A directed and weighted communication topology is taken into account, and the phenomenon of uncertainties is reflected in both modelling and inner coupling matrices. In order to save communication resources, a new and practical event-triggered communication mechanism with an asynchronous sampling manner is developed, with which the Zeno behaviour can be absolutely avoided. Then, based on the presented event-triggered strategy, a pinning control protocol is proposed to reduce the frequency of controller updates and the computational burden. The problems on the minimal number and which of the nodes should be chosen are addressed. By Lyapunov stability theory, sufficient conditions are deduced to ensure the underlying network achieves global robust ${H_\infty }$ pinning synchronization. Finally, numerical examples are provided to verify the effectiveness of the new design techniques. [ABSTRACT FROM AUTHOR]

To better understand the correlation between network topological features and the robustness of network controllability in a general setting, this paper suggests a practical approach to searching for optimal network topologies with given numbers of nodes and edges. Since theoretical analysis seems impossible at least in the present time, exhaustive search based on optimization techniques is employed, firstly for a group of small-sized networks that are realistically workable, where exhaustive means 1) all possible network structures with the given numbers of nodes and edges are computed and compared, and 2) all possible node-removal sequences are considered. A main contribution of this paper is the observation of an empirical necessary condition (ENC) from the results of exhaustive search, which shrinks the search space to quickly find an optimal solution. ENC shows that the maximum and minimum in- and out-degrees of an optimal network structure should be almost identical, or within a very narrow range, i.e., the network should be extremely homogeneous. Edge rectification towards the satisfaction of the ENC is then designed and evaluated. Simulation results on large-sized synthetic and real-world networks verify the effectiveness of both the observed ENC and the edge rectification scheme. As more operations of edge rectification are performed, the network is getting closer to exactly satisfying the ENC, and consequently the robustness of the network controllability is enhanced towards optimum. [ABSTRACT FROM AUTHOR]

In this paper, a novel adaptive second-order sliding mode (SOSM) control method is proposed by combining a new adaptive strategy with the backstepping-like technique. The new adaptive strategy is first constructed by means of the equivalent control for which a sliding-mode-based filter is employed rather than the widely-used low-pass filter such that the parameter restriction under the usage of low-pass filter can be relaxed. Then, by applying the proposed adaptive strategy and the idea of adding a power integrator, an adaptive SOSM method is established to finite-time stabilize the sliding variables. The feature of the proposed SOSM method lies in that the gain will vary with the size of the lumped uncertainty so as to avoid the overestimation of the gain. The stability analysis is given based on the finite-time Lyapunov theory. The theoretical results are finally applied to the voltage regulation problem of a Buck converter. [ABSTRACT FROM AUTHOR]

In this paper a three-stage dynamic-biased CMOS amplifier is designed with a robust optimization of its settling-time performance. The methodology studies the stability of a third order system through the so-called “separation factors” and analyzes the settling time performance through the use of contour plots, in order to define a suitable design strategy. The approach is experimentally validated through the design of a three-stage amplifier with a new compensation network. Monte Carlo simulations as well as experimental results on an integrated prototype demonstrate the validity of the proposed method. [ABSTRACT FROM PUBLISHER]

Visual feature detection has been widely used in many computer vision applications, with increasing concern on feature robustness, processing speed, and power efficiency. In comparison with popular feature detection algorithms, affine-SIFT achieves the strongest robustness on the image illumination, image rotation, and image scale transformation, but exhibits extreme high computation complexity. To improve its computing efficiency, this work first proposes three hardware optimization methods to address three main performance bottlenecks. The first method is the reverse affine-based pipelined computing with optimized memory accessing. The second method is about stream processing with full parallel Gaussian pyramid. The third method is the rotation invariant binary pattern based feature vector generation. Then by incorporating these three optimization methods, this paper designs a high-efficient pipelined and parallel hardware architecture with optimized parallel memory accessing. Postlayout simulations using TSMC 65-nm 1P9M low power process show that this work achieves a processing speed of 97 fps at 1080p (1000 feature points per frame on average) under 200 MHz, with power consumption at 300 mW. In comparison, its computing efficiency (1005.6K pixels/s at 1 MHz) and power efficiency (670.5K pixels/s at 1 mW) are higher than state-of-the-art works and it is more promising for broad vision applications especially the embedded vision and mobile vision applications. [ABSTRACT FROM AUTHOR]

This paper focuses on the development of a delta operator Kalman filter and its convergence analysis. The delta operator Kalman filter is designed to estimate the state vectors of a delta operator system. Note that the designed delta operator Kalman filter can express both continuous-time and discrete-time cases. Then, the convergence analysis of the delta operator Kalman filter is also investigated by using Lyapunov approach in delta domain. Furthermore, this paper gives fundamental results for the analysis and application of the delta operator Kalman filter as a state observer in an inverted pendulum model. Some experimental results of an inverted pendulum on a laboratory-scale setup are presented to illustrate the effectiveness of the designed Kalman filter and its implementation. [ABSTRACT FROM PUBLISHER]

It is well known that multi-agent systems (MASs) are ubiquitous in natural and artificial systems. This paper aims at bridging the gap between transmission noise and sampled data for robust consensus of MASs. In detail, we have developed a theoretical framework for analyzing the robust consensus of MASs with sampled-data controllers and transmission noises. Using the delay-input and discretization approaches, we obtain two sufficient conditions on the existence of sampling periods and controller parameters for robust consensus of MASs, respectively. In particular, we deduce the estimates of the convergence speeds of consensus errors for the above two methods. Finally, numerical simulations are also given to validate our theoretical results. [ABSTRACT FROM AUTHOR]

Memristors, initially introduced in the 1970s, have received increased attention upon successful synthesis in 2008. Considerable work has been done on modeling and applications in specific areas, however, very little is known on the potential of memristors for control applications. Being nanoscopic variable resistors, it is intuitive to think of using them as a variable gain. The main contribution of this paper is the development of a memristive analog gain control framework and theoretic foundation of a control strategy which can be implemented using this framework. Analog memristive controllers may find applications in control of large array of miniaturized devices where robust and adaptive control is needed due to parameter uncertainty and ageing issues. [ABSTRACT FROM AUTHOR]

This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry \times \,32 -bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low- \text {V}_{\mathrm {t}} ) CMOS process. A four-transistor read port is presented that permits the design of low-capacitance dynamic local bitlines (LBLs). Switching power in the LBLs and the LBL precharge buffer is thereby reduced. Based on extensive simulation results, the proposed read port is recommended for use in wide-worded RFs, which employ a wide dynamic-OR structure at the LBL stage. The proposed RF outperforms the conventional design in terms of power consumption for frequencies exceeding 3-GHz. The read port exploits intrinsic capacitive coupling to achieve robust operation over a wide voltage range. The architecture of the read port simultaneously enhances robustness of the dynamic bitline by 58.8% as compared to the conventional low- \text {V}_{\mathrm {t}}$ bitline. [ABSTRACT FROM PUBLISHER]

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty. [ABSTRACT FROM AUTHOR]

Robust synchronization problem is a key issue in chaotic circuits and nonlinear systems. This paper is concerned with robust synchronization problem of polynomial nonlinear system affected by time-varying uncertainties on topology, i.e., structured uncertain parameters constrained in a bounded-rate polytope. Via partial contraction analysis, novel conditions, both for robust exponential synchronization and for robust asymptotical synchronization, are proposed by using parameter-dependent contraction matrices. In addition, for polynomial nonlinear system, this paper introduces a new class of contraction matrix, i.e., homogeneous parameter-dependent polynomial contraction matrix (HPD-PCM), by which tractable conditions of linear matrix inequalities (LMIs) are provided via affine space parametrizations. Furthermore, the variant rate margin for robust asymptotical synchronization is, for the first time, proposed and investigated via handling generalized eigenvalue problems (GEVPs). A set of representative examples demonstrate the effectiveness of proposed method. [ABSTRACT FROM AUTHOR]

This paper considers chaos synchronization and chaos-based secure communication problems based on high-gain sliding mode unknown input observers when the observer matching condition is not satisfied to the drive signal. An auxiliary drive signal vector which satisfies the observer matching condition is introduced and an adaptive and robust observer is developed by using the auxiliary drive signal directly to not only estimate the states but also adjust adaptively the unknown parameters and the Lipschitz constants of the nonlinear terms. A high-gain sliding mode observer is considered to exactly estimate both the auxiliary drive signals and their derivatives in a finite time only based on the original drive signal. The combination of the adaptive and robust observer and the high-gain sliding mode observer becomes the receiver in chaos-based secure communication discussion. A kind of information signal recovering method is developed based on both the state synchronization and exact estimates of the derivatives of the auxiliary drive signals. Finally, a numerical simulation example is given to illustrate the effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new deadbeat dissipative filter with a finite impulse response (FIR) structure for linear discrete-time systems with external disturbance; this filter is called a deadbeat dissipative FIR filter (DDFF). The new filter ensures (Q,S,R)\text--\alpha-dissipativity and the deadbeat property based on three slack matrix variables. By tuning the weighting parameters provided by the (Q,S,R)\text--\alpha-dissipativity in the proposed DDFF, we present H\infty and passive FIR filters in a unified framework and investigate ways of improving the l2 stability, bounded-disturbance bounded-error stability, and robustness of FIR filters. The gain matrix of the proposed DDFF is obtained by solving a convex problem using the linear matrix inequality approach. Two numerical examples are provided to demonstrate the effectiveness and advantages of the obtained theoretical results. [ABSTRACT FROM PUBLISHER]

The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions. [ABSTRACT FROM AUTHOR]

A disturbance observer-based control (DOBC) approach is proposed in this paper for control design and qualitative robustness analysis of PWM-based DC-DC buck power converters. A disturbance compensation gain is constructed for the composite control algorithm to cancel the unmatched uncertainties in the output voltage channel. Rigorous criterion is provided to show the quantitative robustness between controller parameters and circuit uncertainties. The DOBC approach delivers not only a promising disturbance rejection performance but also a superior property of tracking performance recovery. The feasibility and efficiency of the proposed approach is validated by experimental results based on LabVIEW real-time control test setup. [ABSTRACT FROM AUTHOR]

This paper addresses the fault detection problem for discrete-time Markovian jump systems with incomplete knowledge of transition probabilities, randomly varying nonlinearities and sensor saturations. For the Markovian mode jumping, the transition probability matrix is allowed to have partially unknown entries, while the cases with completely known or completely unknown transition probabilities are also investigated as two special cases. The randomly varying nonlinearities and the sensor saturations are introduced to reflect the limited capacity of the communication networks resulting from the noisy environment, probabilistic communication failures, measurements of limited amplitudes, etc. Two energy norm indices are used for the fault detection problem in order to account for, respectively, the restraint of disturbance and the sensitivity of faults. The purpose of the problem addressed is to design an optimized fault detection filter such that 1) the fault detection dynamics is stochastically stable; 2) the effect from the exogenous disturbance on the residual is attenuated with respect to a minimized \cal H\infty-norm; and 3) the sensitivity of the residual to the fault is enhanced by means of a maximized \cal H\infty-norm. The characterization of the gains of the desired fault detection filters is derived in terms of the solution to a convex optimization problem that can be easily solved by using the semi-definite programme method. Finally, a simulation example is employed to show the effectiveness of the fault detection filtering scheme proposed in this paper. [ABSTRACT FROM AUTHOR]

This paper tackles the problem of finite frequency $\mathcal H_{\infty }$ filtering design for polytopic uncertain discrete-time systems using past output measurements. The noise is assumed to be restricted in a finite frequency range, i.e., the low, middle, or high frequency range. The objective is to design an admissible filter with past output measurements of the system, guaranteeing the asymptotic stability of the filtering error system with a prescribed finite frequency $\mathcal H_{\infty }$ disturbance attenuation level. Based on past output measurements together with the parameter-dependent Lyapunov function and projection lemma, a new sufficient condition for robust finite frequency $\mathcal H_{\infty }$ performance is first derived, and then, the filter synthesis is developed. It is shown that the filter gains can be obtained by solving a set of linear-matrix-inequalities. Finally, two examples are given to demonstrate the advantages and effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper proposes a new 10-transistor (10T) bitcell for robust operations at subthreshold voltages without any boost circuitry. Features of the proposed bitcell include: 1) differential pre-discharged bit-lines and a pair of decoupled access ports to resist disturbance; 2) footed latch for write assist; 3) spare latch-foot to fight against half-select disturbances; and 4) highly stacked pull-down structure to reduce both leakage and power. A bit-interleaved SRAM macro, constructed with the proposed 10T bitcell, is fabricated in 28 nm CMOS. The power consumption has been measured as 90 nW for 30 kHz access at 0.25 V, and 41 nW for retention at 0.20 V, of which the leakage is 31% better than the state-of-the-art design. [ABSTRACT FROM AUTHOR]

The output voltage regulation problem of a PWM-based dc-dc buck converter under various sources of uncertainties and disturbances is investigated in this paper via an optimized active disturbance rejection control (ADRC) approach. Aiming to practical implementation, a new reduced-order generalized proportional integral (GPI) observer is first designed to estimate the lumped (possibly time-varying) disturbances within the dc-dc circuit. By integrating the disturbance estimation information raised by the reduced-order GPI observer into the output prediction, an optimized ADRC method is developed to achieve optimized tracking performance even in the presence of disturbances and uncertainties. It is shown that the proposed controller will guarantee the rigorous stability of the closed-loop system, for any bounded uncertainties of the circuit, by appropriately choosing the observer gains and the bandwidth factor. Experimental results illustrate that the proposed control solution is characterized by improved robustness performance against various disturbances and uncertainties compared with traditional ADRC and integral model predictive control (MPC) approaches. [ABSTRACT FROM PUBLISHER]

In this paper, we consider the modeling and (robust) control of a DC-DC Boost converter. In particular, we derive a mathematical model consisting of a constrained switched differential inclusion that includes all possible modes of operation of the converter. The obtained model is carefully selected to be amenable for the study of various important robustness properties. For this model, we design a control algorithm that induces robust, global asymptotic stability of a desired output voltage value. The guaranteed robustness properties ensure proper operation of the converter in the presence of noise in the state, unmodeled dynamics, and spatial regularization to reduce the high rate of switching. The establishment of these properties is enabled by recent tools for the study of robust stability in hybrid systems. Simulations illustrating the main results are included. [ABSTRACT FROM AUTHOR]

In recent years, the popularity of electric vehicles (EVs) has been rapidly expanding, thanks to the government’s supportive policies. However, managing EV’s en-route re-charge activities under different operation scenarios is still a critical issue, when the EV’s limited driving range and long re-charge time are concerned. In this paper, an EV flow distribution problem is formulated for the guidance of EV’s re-charge activities. The problem manipulates EV flows directly with the consideration of EV’s queuing and re-charge delay at charging stations, which makes it greatly different from the classic problems. To solve the problem effectively, a dedicated flow distribution algorithm (FDA) is devised. Furthermore, based on the centrality properties in the context of complex network science, the interdependence of EV flow distribution and charging resource allocation is investigated. Simulation results show that a proportional allocation of chargers to nodes with high weighted betweenness leads to the most efficient flow distribution. In addition, robustness is introduced to measure the flow distribution solution’s endurance under EV drivers’ ignorance of guidance. The comparison among centrality-based allocations and an optimization-based allocation reveals that efficiency and robustness are two conflicting properties in flow distribution, dependent on the allocation of charging resources. [ABSTRACT FROM AUTHOR]

This paper is concerned with the attack-resilient event-triggered controller design problem of a DC microgrid with multiple nonlinear constant power loads and intermittent denial-of-service (DoS) attacks. First, for a resource efficiency purpose, an event-triggering communication scheme is delicately devised in such a way to only invoke the data transmission over the communication line when the DoS attack is inactive. Second, via characterizing the DoS active and inactive time intervals, a new switching piecewise system model for the nonlinear DC microgrid system is presented. Third, a numerically efficient design criterion on the existence of the desired attack-resilient event-triggered controller is established. It is further shown that various performance indices including resource efficiency, attack resilience, robustness against disturbance, sampling performance of the DC microgrid system can be evaluated in a unified framework. Finally, an illustrative example is given to verify the effectiveness of the proposed control design method for the DC microgrid. [ABSTRACT FROM AUTHOR]

This study proposes a novel dynamic event-triggered impulsive control (ETIC) scheme to study the exponential stabilization of general stochastic nonlinear systems, where the impulsive sequence is determined by a dynamic event-triggered mechanism. The dynamic ETIC can effectively reduce controller updates and significantly save energy under the same decay rate compared to traditional static event-triggered impulsive generators. Additionally, there is a guaranteed positive minimum inter-event time for each sample path solution of systems. Furthermore, the proposed dynamic ETIC scheme is employed to stabilize stochastic complex networks based on the graph theory and the Lyapunov method. Finally, we provide two illustrative examples to verify the effectiveness and correctness of the proposed dynamic ETIC scheme. [ABSTRACT FROM AUTHOR]

This paper presents a family of robust set-membership normalized subband adaptive filtering (RSM-NSAF) algorithms for acoustic echo cancellation (AEC). By using a new robust set-membership error bound, the RSM-NSAF algorithm obtains improved robustness against impulsive noises and decreased steady-state misalignment relative to the conventional set-membership NSAF (SM-NSAF) algorithm. To exploit the sparsity of the impulse response, the L0 norm constraint robust set-membership NSAF ( L0 -RSM-NSAF), robust set-membership improved proportionate NSAF (RSM-IPNSAF), and L0 norm constraint robust set-membership improved proportionate NSAF ( L0 -RSM-IPNSAF) algorithms are derived by minimizing a differentiable cost function that utilizes the Riemannian distance between the updated and previous weight vectors as well as the L0 norm of the weighted updated weight vector. Simulations in AEC application confirm the improvements of the proposed algorithms in performance. [ABSTRACT FROM PUBLISHER]

The prevalence of wireless networks has made the long-term need for communications security more imperative. In various wireless applications, images and/or video constitute critical data for transmission. For their copyright protection and authentication, watermarking can be used. In many cases, the cost of wireless nodes must be kept low, which means that their processing and/or power capabilities are very limited. In such cases, low-cost hardware implementations of digital image/video watermarking techniques are necessary. However, to end up with such implementations, proper selection of watermarking techniques is not enough. For this reason, in this paper, we introduce computation optimizations of the implemented algorithm to keep the integer part of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. In addition, further analysis is performed to reduce quantization error. Three different hardware-architecture variants, two for image watermarking and one for video (pipelined), are proposed, which reutilize the already small arithmetic units in different computation steps, to further reduce implementation cost. The proposed designs compare favorably to already existing implementations in terms of area, power, and performance. Moreover, the watermarked images’/frames’ errors, compared to their floating point counterparts, are very small, while robustness to various attacks is high. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel robust H∞ optimization approach to the design of digital filters for calibrating 2.1 cascaded sigma-delta (SD) modulators. The main contribution of this paper consists of two parts. First, we develop a new filter design technique based on linear matrix inequalities applied to a model-matching problem with polytopic uncertainties in parameters. The advantage of the proposed method is that it leads to an optimal, less conservative, solution to the robust H∞ filtering problem. The second contribution involves the application of!the proposed robust filter design scheme to correct for inevitable and unwelcome analog imperfections typically associated with cascaded SD modulators. For numerical illustration we concentrate on the 2-1 architecture. Simulation results for a range of parameter excursions suggest that our robust H∞ filter guarantees an improved signal-to-noise ratio performance over the nominal filter. [ABSTRACT FROM AUTHOR]

In this paper, we formulate a new type of Monte Carlo problem for circuits. Specific results are given for the class of resistive networks and open research problems are indicated for more general cases. Given lower and upper bounds on the value of each resistor but no probability distribution, we consider the problem of estimating appropriate probabilistic measures of performance. In view of the fact that no a priori probability distributions for the uncertain resistors are assumed, a certain type ‘distributional robustness’ is sought. To this end, a new paradigm from the robustness literature is particularized to these circuits. Some of the performance bounds obtained via this new approach differ considerably from those which result from a more conventional Monte Carlo simulation. [ABSTRACT FROM AUTHOR]

In this paper, an efficient all-digital demodulator in digital communication receivers is proposed and implemented on a reconfigurable hardware platform in order to compensate timing and carrier phase offset. In the proposed design, a feedforward architecture which has better stability and performance than traditional feedback architectures is used in the timing synchronization loop. To mitigate the problem of oversampling rate of feedforward synchronizer, an innovative parallel demodulator architecture is presented which is optimized for high speed transmissions. This proposed architecture results in asynchronous data sampling where there is no need to adjust sampling rate of the analog to digital converter with an external feedback. To achieve good stability conditions in the presence of loop delay in carrier recovery loop, an appropriate compensation method using a novel Smith predictor is utilized. Since the delay compensation technique is applied, the proposed architecture is well suited for pipelined VLSI implementations. The proposed architecture is used to implement M-QAM digital communication receiver on a Xilinx Virtex-7 FPGA platform achieving a clock rate of 612 MHz. Implementation results show that our design has a good performance for different modulation orders as well as excellent robustness against loop delays and variations in the loop. [ABSTRACT FROM PUBLISHER]

In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing. [ABSTRACT FROM PUBLISHER]

This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no analog reference generation and distribution by leveraging the implicit timing reference set by the gate delay in the sense amplifier. Monte Carlo simulations in 65 nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to CVS. This is achieved at the cost of less than 1% area penalty and 13–14% performance degradation, and insignificant (2%) energy penalty when designed at iso-area (minimum delay). Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff. [ABSTRACT FROM AUTHOR]

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate. This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness. From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (0.75–1.2 V) compared with the conventional voltage sensing scheme. This is achieved at 0.3% area overhead, less than 15% performance degradation, and less than 25% energy penalty. Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6–10% compared with the standalone DR. [ABSTRACT FROM AUTHOR]

This paper deals with the problem of robust adaptive synchronization of dynamical networks with stochastic coupling by means of evolutionary algorithms. The complex networks under consideration are subject to: 1) the coupling term in a stochastic way is considered; 2) uncertainties exist in the node's dynamics; and 3) pinning distributed synchronization is also considered. By resorting to Lyapunov function methods and stochastic analysis techniques, the tasks to get the distributed robust synchronization and distributed robust pinning synchronization of dynamical networks are solved in terms of a set of inequalities, respectively. The impacts of degree information, stochastic coupling, and uncertainties on synchronization performance, i.e., mean control gain and convergence rate, are derived theoretically. The potential conservativeness for the distributed robust pinning synchronization problem is solved by means of an evolutionary algorithm-based optimization method, which includes a constraint optimization evolutionary algorithm and a convex optimization method and aims at improving the traditional optimization methods. Simulations are provided to illustrate the effectiveness and applicability of the obtained results. [ABSTRACT FROM AUTHOR]

Aimed at the problem that the unmanned aerial vehicle (UAV) close formation cannot maintain its desired formation shape due to the wind field disturbances, a novel distributed adaptive control approach is proposed to counteract the lateral and forward distance errors caused by uncertain wind field disturbances. Firstly, based on the “leader-follower” model, an adaptive control law is designed to accurately estimate the magnitude and direction of the wind in 3-D space. Then, the distance errors caused by uncertain wind field disturbances is counteracted by controlling UAV relative movement. Moreover, their velocity can keep constant to achieve the desired formation shape. Additionally, the signals of the closed-loop system are semi-globally practical finite-time stable (SGPFS). Finally, the simulation results show that the proposed adaptive control algorithm has good robustness, which provides a theoretical basis for engineering practice. [ABSTRACT FROM AUTHOR]

In this paper, a novel, high precision lowpass LC ladder synthesis algorithm is presented. The new algorithm directly works on the driving point input immitance function which describes the lowpass LC ladder in resistive termination. The crux of the idea is that, at each step of the proposed method, a simple pole at infinity is removed then, the remaining immitance function is corrected using the parametric method. Parametric method warrants the exact lowpass LC ladder nature of the remaining immitance function. Thus, at the end of the synthesis process, a lowpass LC ladder is obtained with high numerical precision. Examples are presented to exhibit the implementation of the synthesis algorithm. A randomly generated driving point input immitance is synthesized with 19 elements yielding a relative error less than 10^-6. Furthermore, numerical robustness of the novel synthesis method is tested. Based on the tests, we can confidently state that, proposed synthesis algorithm can safely extract more than 40 elements from the original immitance function with a relative error less than 10^-2. Newly developed synthesis algorithm is coded on MatLab environment and it is successfully combined with the “Real Frequency-Direct Computational Technique” to construct practical impedance matching networks. [ABSTRACT FROM PUBLISHER]

This paper finds and investigates the application of fixed-event-time based discretized sliding mode (DSM) controller in dc-dc buck converter, to achieve fast transient response and high robustness under wide parameters variation. We show that how these can be achieved by integrating the concept of Utkin's equivalent control law and discontinuous border-collision bifurcation (DBCB) theory developed for 2-D discontinuous piecewise smooth (PWS) maps. Moreover, based on derived 2-D discontinuous maps of DSM-controlled converter, we investigate its inherent steady-state dynamical properties or bifurcation behaviors under different parameters variation. Numerically as well as experimentally obtained bifurcation diagrams are then presented to show the domains of existence of different oscillatory modes and their sequence of occurrence. Such phenomena are not only useful to study the robustness of the system but may also facilitates to design the input filter with fast transient response. The performance of DSM controller is experimentally verified and compared with hysteresis and classical peak current-mode controller. [ABSTRACT FROM PUBLISHER]

In this paper, the robust information fusion Kalman filtering problem is considered for multi-sensor systems with parameter uncertainties, randomly delayed measurements and sensor failures. The stochastic parameter perturbations are included in the state space models such that the proposed fusion estimator has robustness for the varying system parameters. For each observation subsystem, multiple binary random variables with known probabilities are introduced to model sensor failures and random delays in the measurements. Without resorting to the augmentation of system states and measurements, a robust optimal recursive filter for each subsystem is derived in the linear minimum variance sense by using the innovation analysis method, and the estimation error cross-covariance matrix between any two subsystems is given recursively. Based on the optimal fusion algorithm weighted by matrices, a robust distributed state fusion Kalman filter is derived for the considered system, and the dimension of the designed filter is the same as the original system, which can reduce computation costs as compared with the augmentation method. Moreover, the performance of the designed fusion filter is dependent on the sensor failure rates. Finally, two illustrative examples are given to show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper we present a framework for robust design of continuous-time ΣΔ modulators. The approach allows to find a modulator which maintains its performance (stability, guar anteed peak SNR, . . .) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time ΣΔ modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework. [ABSTRACT FROM PUBLISHER]

In this paper, the H\infty theory is introduced to investigate the robustness and design of synchronization nonlinear coupled network. The H\infty synchronization performance is defined as the disturbance attenuation ability for a synchronized coupled network. To measure the H\infty synchronization performance of a nonlinear coupled network, we need to solve a Hamilton–Jacobi inequality (HJI), which is hard to treat directly. Hence, a Takagi–Sugeno fuzzy system is employed to approximate the nonlinear coupled network, so that the HJI can be replaced by a set of linear matrix inequalities. Furthermore, based on this H\infty synchronization performance, a robust nonlinear coupled network with a prescribed H\infty synchronization performance can be designed for a given network topology. In the robust H\infty synchronization network, our design task is to specify the minimum coupling strengths of the corresponding links in the network topology such that the coupled network cannot only synchronize but also attenuate the external disturbance below a prescribed level. Since the design of robust H\infty synchronization network leads to a set of bilinear matrix inequalities (BMIs), a two-step algorithm is proposed to solve the BMI-constrained optimization problem. The time-delay effect on the synchronization of coupled network is also discussed. [ABSTRACT FROM PUBLISHER]

In this paper, we address the problem of analyzing the performance of an electrical circuit in the presence of uncertainty in the network components. In particular, we consider the case when the uncertainties are known to be bounded and have probabilistic nature, and aim at evaluating the probability that a given system property holds. In contrast with the standard Monte Carlo approach, which utilizes random samples of the uncertainty to estimate "soft" bounds on this probability, we present a methodology that provides "hard" (deterministic) upper and lower bounds. To this aim, we develop an iterative algorithm, based on a property oracle, which is shown to converge asymptotically to the true probability of property satisfaction. Construction of the property oracles for specific applications in circuit analysis is explicitly presented. In particular, we study in full detail the problems of assessing the probability that the gain of a purely resistive network does not exceed a prescribed value, and of evaluating the probability of stability of an uncertain network under parameter variations. The paper is accompanied by illustrating examples and extensive numerical simulations. [ABSTRACT FROM AUTHOR]

Near field wideband beamformers for microphone arrays have wide applications, such as hands-free telephony, hearing aids, and speech input devices to computers. The existing design approaches for nearfield wideband beamformers are highly sensitive to errors in microphone array characteristics, i.e., microphone gain, phase, and position errors, as well as sound speed errors. In this paper, a robust design approach for nearfield wideband beamformers for microphone arrays is proposed. The robust nearfield wideband beamformers are designed based on the minimax criterion with the worst case performance optimization. The design problems can be formulated as second-order cone programming and be solved efficiently using the well-established polynomial time interior-point methods. Several interesting properties of the robust nearfield wideband beamformers are derived. Numerical examples are given to demonstrate the efficacy of the proposed beamformers in the presence of errors in microphone array characteristics. [ABSTRACT FROM AUTHOR]

We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1–2-GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1- and 2-GHz clock frequency, respectively. [ABSTRACT FROM AUTHOR]

We solve a robust receding horizon finite impulse response (FIR) filtering problem in a discrete-time state space in three frequency regions under severe disturbances. Novel design conditions are derived for the finite frequency region FIR filter, called FFFF or 4F, in terms of the linear matrix inequality and equality constraint, such that the 4F ensures the H\infty performance and deadbeat property. The 4F attenuates the effects of disturbances in the user-given low-, middle-, and high-frequency regions. The new design conditions, which do not involve the equality constraint, are also investigated. An example of applications for the $F$ -404 turbofan engine system demonstrates the much better performance of the proposed 4F compared with the existing entire frequency FIR filter and the finite frequency region infinite impulse response filter. [ABSTRACT FROM AUTHOR]

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/ $f$ noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/ $^\circ \text{C}$ supply and temperature sensitivity are obtained, respectively. [ABSTRACT FROM AUTHOR]

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop. [ABSTRACT FROM PUBLISHER]

In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal nodes and output node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch. [ABSTRACT FROM PUBLISHER]