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The DC-DC converter severs as one of the crucial components in DC microgrid applications. In this paper, a novel low frequency current-mode control strategy is proposed to improve overshoot suppression performance for the boost converter against load current and source voltage disturbances. The control strategy is presented as a cascade dual-loop structure composed of a dynamic current-loop controller with asymmetric saturation and a PI form voltage-loop controller. With the low frequency information of disturbances, the designed dynamic current-loop controller delivers not only promising disturbance suppression but also superior reference current tracking. Simulation and experiment results are provided to illustrate the superiority of the proposed strategy on overshoot suppression. [ABSTRACT FROM AUTHOR]

There are practical applications requiring the wireless power transfer (WPT) system to supply multiple output voltages to a variety of loads. In this paper, in order to achieve this goal, multiple double T resonant circuits are connected to the common port of the receiver side. Based on the modeling and analysis of the double T resonant circuit, it is found that the load-independent output and input zero phase angle (ZPA) can be derived. The proposed WPT system presents the following merits: 1) output voltages are load independent and can be controlled synchronously against the disturbance from input DC source and mutual coupling by using only one closed loop; 2) the output voltages can be adjusted individually to different levels by configuring circuit parameters; 3) only passive components are used to achieve multiple outputs. The power loss can be reduced due to the parasitic resistance of the passive component is very small and can be negligible; and 4) the reactive power losses are minimized due to the input ZPA of the system. An experimental prototype with two output channels is built, based on which the load independent and the controllable characteristics of the output voltages are verified. [ABSTRACT FROM AUTHOR]

The growth of IoT applications requires DC-DC converters to have small printed circuit board (PCB) areas and high efficiency over a wide load range. A multi-mode operation of DC-DC converters, therefore, is often necessary to achieve this high efficiency over a wide load range. This paper introduces a tri-mode DC-DC buck converter for IoT applications. The tri-mode operation with PWM, PFM, and multiple-sawtooth PWM (MSPWM) modes helps to retain the high efficiency over the wide load range. The MSPWM mode also enhances a noise margin of the converter, ensuring a regular switching operation at an ultra-light load condition. With a load current prediction scheme, the proposed tri-mode converter requires neither additional load current sensor nor multiple mode controllers. In addition, a soft-start operation is employed to prevent an in-rush current. The proposed tri-mode buck converter has been fabricated through a 0.18- $\mu \text{m}$ CMOS process with a chip area of 0.97 mm $\times0.88$ mm. A load-dependent seamless mode transition is realized, and a maximum converter efficiency of 91% has been measured with a 7.4-MHz switching frequency. [ABSTRACT FROM AUTHOR]

In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J−1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., $Z(f_{0})=R_{\mathrm{ opt}}+jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=-j({3}\pi /{8})R_{\mathrm{ opt}}$), whereas the second MN realizes the optimal impedances of class-J−1 PAs (i.e., $Z(f_{0})=R_{\mathrm{ opt}}-jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=j({3}\pi /{8})R_{\mathrm{ opt}}$). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of $R_{\mathrm{ opt}}$. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two proof-of-concept class-J and class-J−1 PAs are designed and implemented in a 0.25- $\mu \text{m}$ GaAs process, where the proposed OMNs are employed in the designed circuits. The manufactured PAs show ≥28 dBm output power, ≥65% drain efficiency, and ≥61% power-added efficiency at 2 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper proposed a high efficiency boost converter targeting thermoelectric generator energy harvesting. The proposed converter adopts the critical conduction mode rather than the discontinuous mode to reduce the conduction loss, which can improve the peak efficiency at high input power. To reduce the minimum input voltage, an adaptive on-resistance switch, which can automatically change the high side and low side on-resistance according to the input voltage, is used. To maximize the output power, a maximum power point tracking circuit is designed to track the internal source resistance. Radio frequency (RF) kick-up and low voltage startup are used to improve the cold start voltage. The proposed converter is implemented in a 0.18- $\mu \text{m}$ standard CMOS process, which occupies a chip area of about 0.48 mm2. Measurement results show that the peak efficiency of the converter can be up to 90.8% and 60% at 180 and 20 mV of the open-circuit voltage, respectively. Owing to the cold startup circuit, the proposed converter can start successfully with 260-mV open-circuit voltage or −16-dBm RF input. Moreover, the open-circuit voltage can be further lowered to 12 mV with 1.5- $\mu \text{W}$ output power after startup. [ABSTRACT FROM AUTHOR]

In this paper a fourth-order Passive Resonant Tank (PRT) is introduced using a topological modification in LLC tank for current-source output applications of Load Resonant Converters (LRCs). The design procedure is based on the output current/input voltage ratio decoupling from the load coefficient. Therefore, output current can be independent of load variation topologically. In this condition, new criterions are applied on the operational frequency and PRT components ratio. Moreover, kVA/kW ratio of the LRC is considered as a comparing index, to optimize the converter size as well as reduction of voltage/current stresses on the PRT components. To reduce the discrete components number, transformer parasitic inductances and bridge capacitors are used as the PRT components. Also, a simple and accurate PWM-based Quasi-Proportional Controller (QPC) is designed to maintain the output current constant against input voltage variations. Minimum reactive power, low circulating and turn-off current, and ZVS of the inverter switches in a wide loads range are obtained as the advantages of the designed LLCC-LRC. Moreover, sinusoidal shape of the PRT input current and minimum switching losses on the rectifier are maintained. Finally, an experimental prototype with 3.5A output current and 93.9% efficiency is presented for results verification. [ABSTRACT FROM AUTHOR]

In this paper, a cascaded form sparse finite impulse response (FIR) filter design algorithm is proposed. By decomposing a filter into two subfilters, the sparse filter design problem is reformulated as a quadratic constrained ${l} _{0}$ -norm minimization problem, which is further transformed to a convex problem through the introduction of a binary masking vector. An iterative forth-and-back search with sequence direction and error direction control is proposed to optimize the binary masking vector by minimizing the distance between the minimax approximation error and the specified upper bound. Experimental results show that the proposed design algorithm can improve the sparsity with comparable or even lower effective filter order. [ABSTRACT FROM AUTHOR]

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented. [ABSTRACT FROM PUBLISHER]

This paper proposes an efficient structure for implementing a linear-phase finite-impulse-response (FIR) filter of an arbitrary order N for the sampling-rate conversion by a rational factor of L/M, where L(M) is the integer upsampling (downsampling) factor to be performed before (after) the actual filter. In this implementation, the coefficient symmetry of the linear-phase filter is exploited as much as possible and the number of delay elements is kept as low as possible while utilizing the following facts. When increasing (decreasing) the sampling rate by a factor of L(M), only every Lth input sample has a nonzero value (only every Mth output sample has to be evaluated). In this way, the number of required multiplications per output sample is reduced approximately by a factor of two compared with the conventional polyphase implementation. The proposed implementation is first illustrated using two examples. Based on these examples, guidelines are then given on how to efficiently realize an Nth-order linear-phase FIR filter for a sampling-rate converter having an arbitrary rational conversion factor L/M. Finally, the implementation complexity of the proposed approach is evaluated and some examples are included, showing the efficiency of the proposed implementation compared with other existing ones. [ABSTRACT FROM PUBLISHER]

We are considering the problem of controlling a DC-DC switched power converter of the Buck type. The converter involves an inherent control limitation; accordingly the control signal (duty ratio) can only take values in the interval (0, 1). In the relevant literature, such a physical control limitation is generally not taken into account when designing the converter regulators. This is only dealt with in the control implementation stage, placing an isolated limiter between the (linear) controller and the controlled system. Furthermore, the presence of such a limiter is generally ignored when analyzing the closed-loop control system. In the present paper, the control signal limitation is dealt with using a nonlinear regulator that involves an internal limiter. The resulting closed-loop control system is shown to be equivalent to a nonlinear feedback involving a linear dynamics block in closed-loop with a nonlinear static element. Using absolute stability tools, sufficient conditions are established for the involved feedback to be L2-stable. If these conditions are respected when choosing the control design parameters then the regulator meets its objectives (closed-loop stability and output reference tracking). It is worth noting that, though the focus is made on a specific power converter, the paper includes an important theoretical dimension that may be of general interest. [ABSTRACT FROM AUTHOR]

Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time Sigma-Delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD. [ABSTRACT FROM AUTHOR]

This paper presents a new free-running-oscillation resonant dc-dc converter with the Class-E oscillator and the Class-E rectifier, along with its design procedure and design curves for any conditions. The proposed converter is a free-running-oscillation system and has no gate-drive circuit to drive the MOSFET. There- fore, the structure of the proposed converter is simpler than that of class E² dc-dc converter. The proposed converter is suitable for a constant voltage and constant power operation under the fixed designed condition. The proposed converter has the ability to achieve a high power-conversion efficiency and low noises under high-frequency operation because of Class-E switching at both the oscillator and the rectifier. We investigate operations of the proposed converter by circuit experiments and show the validity of the design curves. This paper denotes two experimental results. One achieves 79.3% power-conversion efficiency under 1.54-W output power at an operating frequency 2.00 MHz. The other does 80.5% under 1.60-W output power at an operating frequency 1.98 MHz. [ABSTRACT FROM AUTHOR]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

The bandwidth achievable by using voltage mode control or current mode control in switch-mode power supply is limited by the switching frequency. Fast transient response requires high switching frequency, although lower switching frequencies could be more suitable for higher efficiency. This paper proposes the use of hysteretic control of the output capacitor (Cout) current to improve the dynamic response of the buck converter. An external voltage loop is required to accurately regulate the output voltage. The design of the hysteretic loop and the voltage loop are presented. Besides, it is presented a non-invasive current sensor that allows measuring the current in the capacitor. This strategy has been applied for DVS (dynamic voltage scaling) on a 5 MHz buck converter. Experimental results validate the proposed control technique and show fast transient response from 1.5 V to 2.5 V in 2 \mus. [ABSTRACT FROM PUBLISHER]

This paper proposes a small-signal model for variable-switching-frequency hysteretic converters operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The model is capable of predicting flip-bifurcation phenomena when the hysteretic converter operates below the CCM/DCM boundary. By developing a discrete-time state-space model of the converter, the z-domain model is derived using the advanced z-transform. Such a tool is suitable to transform in the z-domain signals varying within a switching cycle. A comparison with exact simulations is provided to validate the proposed model. The propagation delay of the feedback control circuit is included due to its significant influence on the low-frequency open-loop gain. Experimental results run on a test chip including a 10-MHz TSMC 0.18\ \mu\m-process hysteretic-mode buck converter are also reported along with the model results. [ABSTRACT FROM PUBLISHER]

This paper proposes combining the standard histogram method with a stimulus identification algorithm in order to test the integral nonlinearity (INL) of a high-resolution analog-to-digital (A/D) converter without a high-quality sine wave. The major problems in the two techniques are explained in order to appreciate the benefits of the combination. The increased INL estimation accuracy is verified with simulations of 16-b A/D converters under different conditions, and experimental results of the INL testing of a 16-b A/D converter are also quoted to support the theory. The simulations and experimental tests show that the INL of 16-b A/D converters can be measured with very simple equipment and that an accurate test stimulus is not necessary. [ABSTRACT FROM AUTHOR]

In this paper, the slow-scale instability in a boost PFC converter under average current mode control is studied via the harmonic balance method and Floquet theory. Systematic and general numerical algorithm of the technique is developed. The objective is to identify instability of the system. If instability exists, the type of bifurcation and the boundaries of slow-scale instability in the parameter space of the system can be found for facilitating the design of such converters. Firstly, based on the fact that the current compensator is designed very well and what we considered is the slow-scale instability, the simplified model of a boost PFC converter under average current mode control is derived. And then, the solution of the simplified model is calculated by using the harmonic balance method. Subsequently, both the stability of the circuit system and the type of bifurcation are identified via Floquet theory. Meanwhile, the critical conditions of the stable operation in the parameter space of the system are given accurately. Finally, experimental results are presented for the verification of the analytical results. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated switched-capacitor power converter for self-powered wireless sensor nodes. The design features an efficient step-down charge-pump power stage and a frequency-programmable digital feedback controller. The subthreshold-region design significantly reduces the power dissipation in the controller. Meanwhile, the programmable switching-frequency digital-pulse-width-modulation control keeps the converter stay at high efficiency, without causing a random noise spectrum. Monolithic implementation effectively suppresses noise and glitches caused by parasitic components due to bonding, packaging, and PCB wiring. Design strategy, system modeling, optimization, and circuit implementation are addressed. An IC prototype was fabricated with a standard 0.35-μm digital CMOS n-well process. It precisely provides a dynamic- voltage-scaling-compatible adjustable power output from 0.8 to 1.5 V and from 400 μW to 7.5 mW. The switching frequency is programmable from 200 kHz to 1 MHz. It achieves 66.7% efficiency with a controller power dissipation of only 147.5 μW. [ABSTRACT FROM AUTHOR]

The dynamics of a zero-average dynamic strategy controlled dc-dc Buck converter, modelled by a set of differential equations with discontinuous right-hand side is studied. Period-doubling and corner-collision bifurcations are found to occur close to each other under small parameter variations. Closer examination of the parameter space leads to the discovery of a novel bifurcation. This type of bifurcation has not been reported so far in the literature and it corresponds to a corner-collision bifurcation of a nonhyperbolic cycle. The bifurcation boundaries are computed analytically in this paper and the system dynamics are unfolded close to the novel bifurcation point. [ABSTRACT FROM AUTHOR]

A new family of a single-switch three-diode dc-dc pulsewidth-modulated (PWM) converters operating at constant frequency and constant duty cycle is presented in this paper. The proposed converters are different from the conventional dc-dc step-up converters, and they posses higher voltage gain with small output voltage ripples. Other advantages of the proposed converters include lower voltage stress on the semiconductor devices, simple structure, and control. Moreover, the reduced voltage stress on the diodes allows using Schottky diodes for alleviating the reverse-recovery current problem, as well as decreasing the switching and conduction losses. The principle of operation, theoretical analysis, and experimental results of one prototype rated 40 W and operating at 94 kHz are provided in this paper to verify the performance of this new family of converters. [ABSTRACT FROM AUTHOR]

To study the stability of a nominal cyclic steady state in power electronic converters, it is necessary to obtain a linearization around the periodic orbit. In many past studies, this was achieved by explicitly deriving the Poincaré map that describes the evolution of the state from one clock instant to the next and then locally linearizing the map at the fixed point. However, in many converters, the map cannot be derived in closed form, and therefore this approach cannot directly be applied. Alternatively, the orbital stability can be worked out by studying the evolution of perturbations about a nominal periodic orbit, and some studies along this line have also been reported. In this paper, we show that Filippov's method—which has commonly been applied to mechanical switching systems—can be used fruitfully in power electronic circuits to achieve the same end by describing the behavior of the system during the switchings. By combining this and the Floquet theory, it is possible to describe the stability of power electronic converters. We demonstrate the method using the example of a voltage-mode-controlled buck converter operating in continuous conduction mode. We find that the stability of a converter is strongly dependent upon the so-called saltation matrix—the state transition matrix relating the state just after the switching to that just before. We show that the Filippov approach, especially the structure of the saltation matrix, offers some additional insights on issues related to the stability of the orbit, like the recent observation that coupling with spurious signals coming from the environment causes intermittent subharmonic windows. Based on this approach, we also propose a new controller that can significantly extend the parameter range for nominal period-1 operation. [ABSTRACT FROM AUTHOR]

This paper reports slow-scale instability in a single-stage power-factor-correction (PFC) power supply, which is a popular design solution for low power applications. The circuit employs a cascade configuration of a boost converter and a forward converter, which share an active switch and operate in discontinuous-conduction mode (DCM), to provide input PFC and tight output regulation. Main results are given by "exact" cycle-by-cycle circuit simulations. The effect of the slow-scale instability on the attainable power factor is illustrated in terms of total harmonic distortion which can be found by taking the fast Fourier transform of the input current. The slow-scale instability usually manifests itself as local oscillations within a line cycle. Based on the critical condition of DCM for the buck converter, the underlying mechanism of such instability is further investigated. It has been found that border collision is the underlying cause of the phenomenon. Moreover, it has been shown that the border collision observed here is effectively a nonsmooth Neimark-Sacker bifurcation. Finally, experimental results are presented for verification purposes. [ABSTRACT FROM AUTHOR]

In this paper, the small-signal mathematical model of a zero-current-zero-voltage-transition (ZCZVT) soft-switching boost power converter is proposed. It shows that the ZCZVT boost converter exhibits better dynamic behavior than the conventional pulsewidth modulated boost converter. The input-to-output voltage conversion ratio of the ZCZVT soft-switching converters lies in a range which is related to the load. Based on the derived model, a classical controller and a modified integral variable structure controller are designed to achieve output voltage regulation and line voltage disturbance rejection. The experimental results regarding converters performances for two controllers are compared by experimental results. [ABSTRACT FROM AUTHOR]

This paper considers a new balanced residue number system (RNS) composed of four low-cost moduli \2^n+1,2^n-1,2^n,2^n-1+1\ for odd n. It is complementary to similar already known balanced 4-moduli set \2^n+1,2^n-1,2^n,2^n+1+1\ (n odd), because it fills the gap in the sparse 8-bit resolution of dynamic ranges available for this class of 4-moduli RNSs. The first ever design methods of residue-to-binary (reverse) converters for this new RNS are proposed. Three versions of the converter, differing in the composition of calculations and hence resulting in different critical delays and energy consumption, are considered. Synthesis results obtained for the 65 nm technology for the dynamic ranges from 11 to 83 bits suggest that delay, power consumption, and area of the new converters are significantly improved w.r.t. the state-of-the-art converters for the above mentioned 4-moduli set and are comparable to those offered by the converters for two other balanced 4-moduli sets \2^n+1,2^n-1,2^n,2^n\pm 1-1\ (n even). [ABSTRACT FROM AUTHOR]

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV. [ABSTRACT FROM AUTHOR]

This paper presents an envelope amplifier solution for envelope elimination and restoration (EER), that consists of a series combination of a switch-mode power supply (SMPS), based on three-level voltage cells and a linear regulator. This cell topology offers several advantages over a previously presented envelope amplifier based on a different multilevel topology (two-level voltage cells). The topology of the multilevel converter affects to the whole design of the envelope amplifier and a comparison between both design alternatives regarding the size, complexity and the efficiency of the solution is done. Both envelope amplifier solutions have a bandwidth of 2 MHz with an instantaneous maximum power of 50 W. It is also analyzed the linearity of the three-level cell solution, with critical importance in the EER technique implementation. Additionally, considerations to optimize the design of the envelope amplifier and experimental comparison between both cell topologies are included. [ABSTRACT FROM PUBLISHER]

Computation of periodic steady state in nonlinear circuits is a key issue. Power electronics converters represent an interesting class of switched nonlinear circuits. The behavior of the converter is obtained by the commutations of the electronic devices which determine the switchings among the different converter modes. Switchings can be classified as external, if forced by directly manipulable control variables, and internal if determined by state dependent conditions. The presence of internal switchings makes it difficult to know a priori the sequence of modes and also open loop steady-state behaviors are difficult to be obtained. In this paper the complementarity modeling framework is proposed as a possible approach for computing periodic steady-state oscillations in power converters with internal switchings. It is shown how linear complementarity systems can be used to model the behavior of a wide class of power converters. The discretization of such model allows to formulate a static complementarity problem whose solution provides the steady-state oscillation of the converter. It is proved that the backward zero-order-hold technique preserves passivity through the discretization and allows to determine the unique solution of the complementarity problem. A resonant converter and a dc/dc voltage-mode controlled buck converter are used as examples. [ABSTRACT FROM PUBLISHER]

This paper presents a wide-range I/O buffer able to transmit and receive signals of 0.9/1.2/1.8/3.3/5.0 V by using a typical 0.18 µm CMOS process. The Dynamic gate bias circuit in the proposed I/O buffer is composed of two voltage converters, an EOS (Electrical Overstress) protector, and standard logic cells. A High voltage detector detects voltage level of VDDIO and then generates several bias voltages to the Dynamic gate bias circuit. By using the Dynamic gate bias generator to generate appropriate gate drives for the triple-stacked MOS transistors in the Output stage, the gate-oxide overstress and hot-carrier degradation are avoided. A Floating N-well circuit in the proposed I/O buffer is used to remove undesirable leakage current paths. The proposed I/O buffer can operate at 10/40/50/40/10 MHz when VDDIO are biased at 5.0/3.3/1.8/1.2/0.9 V, respectively. The maximum speed is 50 MHz given a 19 pF load. The maximum static power consumption is merely 3.9 µW justified by the measurements on silicon. [ABSTRACT FROM AUTHOR]

This paper reports the bifurcation phenomena in a dc-dc converter governed by a pulse skipping modulation (PSM) scheme, which is normally used to improve efficiency under light load condition. It is shown that the discrete-time model of the system takes the form of a discontinuous map, where the discrete-time state space is piecewise smooth, divided into five regions, each with a different functional form and separated by four borderlines. One additional borderline is considered to identify an infeasible region during a PSM operation. For a restricted operating region, we show that the system is described by a one-dimensional discontinuous map; otherwise it is a combination 1-D and 2-D forms. We derive the conditions for the existence and stability of different periodic orbits. We observe a period-adding cascade in which the periodicity varies non-monotonically exhibiting abrupt changes in the spectral composition for a smooth parameter variation. The proposed method may be useful for modeling and analysis of other dc-dc converter topologies governed by a PSM operation. [ABSTRACT FROM AUTHOR]

This paper presents a novel decorrelating design-for- digital-testability (D³ T) scheme for Σ - Δ modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Σ - Δ modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D³T scheme has the potential to test moderate nonlinearity. The proposed D³T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests. [ABSTRACT FROM AUTHOR]

This paper proposes a modification for the symbolic synthesis method of analog circuits using admittance matrix expansion. The modification involves a generalization of the synthesis approach to employ mirror elements (voltage mirrors and current mirrors) in the admittance matrix expansion and ideal description of active elements, rather than using only nullor elements (nullators and norators). Accordingly, more alternative ideal representations, based on nullor-mirror elements, can be realized and a wide range of active elements can be used in the circuit synthesis. Systematic synthesis of the CCII-based generalized impedance converters (GICs) is presented as an application example to illustrate the potential of this generalized approach. Multiple equivalent nullor-mirror realizations for the GIC could be extracted easily, by virtue of using mirror elements in the admittance matrix expansion. Consequently, numerous circuit realizations, spanning various combinations of CCII types, have been generated in a simple and direct way. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-voltage switching (ZVS) buck converter with a tapped inductor (TI) is proposed. This converter improves the conventional tapped inductor critical conduction mode buck converters that have the ZVS operation range determined by the TI turn ratios. It includes another soft switching range extension method, the current injection method, which gives an additional design freedom for the selection of the turn-ratios and enables the optimal design of the winding ratio of the TI so that the efficiency may be maximized. This soft-switching buck converter is suitable for wide input range step-down applications. The principle of the proposed scheme, analysis of the operation, and design guidelines are included. Experimental results of the 100-W prototype dc-dc converter are given for hardware verification also. Finally, based on the proposed soft-switching technique, a new soft-switching topology family is derived. [ABSTRACT FROM AUTHOR]

Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. They are widely used in modular multipliers and residue-to-binary converters and in implementing other residue arithmetic operations such as scaling. In this paper, a methodology for designing power-delay-area-efficient modular adders based on carry propagate addition is presented. The binary representational characteristics of the modulus are exploited to allow the sharing of hardware in a fast modular adder topology. VLSI implementation results using 0.13-μm standard-cell technology, together with a theoretical analysis, show that this approach produces adders that offer efficient tradeoffs when compared with the fastest through to the smallest generic modular adders in the literature. [ABSTRACT FROM AUTHOR]

In this paper, reverse converters for two recently proposed four-moduli sets {2n - 1,2n, 2n + 1,2n+1 - 1 } and {2n - 1,2n, 2n + 1,2n+1 + 1 } are described. The reverse conversion in the three-moduli set {2n - 1,2n, 2n + 1,2n+1 + 1 } has been optimized in literature. Hence, the proposed converters are based on two new moduli sets {(2n(22n-1)),2n+1-1} and {(2n(22n-1)),2n+1+1} and use mixed radix conversion. The resulting designs do not require any ROM. Both are similar in their architecture except that the converter for the moduli set {2n - 1,2n, 2n + 1,2n+1 + 1 } is slightly complicated due to the difficulty in performing reduction modulo (2n+1 + 1) as compared with modulo (2n+1 - 1). The proposed conversion techniques are compared with earlier realizations described in literature with regard to conversion time as well as area requirements. [ABSTRACT FROM AUTHOR]

Power factor corrected (PFC) rectifiers, active power filters (APFs), static VAR compensators (STATCOM), and grid-connected inverters (GCI) are indispensable elements in distributed generation power systems. PFC rectifiers are essential for load side harmonic and reactive power correction, APFs can suppress the harmonics generated by nonlinear loads or sources, STATCOMs can control the power flow in the grid, while GCIs are the key elements bridging the renewable energy sources and the power grid. Previous theory and experiments have demonstrated that one-cycle control is capable of controlling all above mentioned three-phase converters, featuring excellent performance, simple circuitry, and low cost. This paper further unifies the control key equations for the previously mentioned converters, which results in a universal solution that realizes all these functions with a same controller. The concept has been verified by a 1-kVA prototype and supported by a series of experimental results. [ABSTRACT FROM AUTHOR]

A novel single-stage isolated high power factor correction (HPFC) converter operating in the discontinuous conduction mode is proposed in this paper. It is an integration of a buck-boost converter with a flyback converter by means of components placement and synchronous switching technology. It can achieve HPFC, tight output voltage regulation and lower voltage stress of the bulk capacitor, which is independent of the loads. The small-signal mathematical model for the proposed converter is derived separately by the averaging method and the current injected equivalent circuit approach. The IsSpice simulations and experimental results successfully verify the dynamics and performances of the proposed converter. [ABSTRACT FROM AUTHOR]

This article presents a high-conversion-ratio (HCR), high-voltage-tolerant (HVT) energy-harvesting battery charger using 0.18- $\mu \text{m}$ standard CMOS for Internet of Things (IoT). To reduce conversion ratio (CR) of inductive power converter and optimize overall power efficiency, the proposed charger cascades a boost converter and reconfigurable charge pump. Different from the high-voltage device, the standard CMOS process has lower parasitic capacitance and on-resistance; therefore, it can reduce switching and conduction loss. The reconfigurable charge pump dynamically changes the number of pumping stages according to the output voltage ($V_{{OUT}}$) by automatic configuration selector (ACS). To manage the limited power from a thermoelectric generator (TEG), the converter works under the discontinuous conduction mode (DCM). The zero-current detector (ZCD) employs an analog comparator with digital offset compensator and digital comparator to control off-time ($T_{{OFF}}$) quickly and accurately. The self-idle constant on-time (SI-COT) and idle mode both control the mechanism, helping to further reduce static power dissipation. As a result, the proposed converter can achieve peak efficiency of up to 76% at a $92\times $ conversion ratio with output power ranging from $10~\mu \text{W}$ to 1.9 mW. The available input voltage ranges are 40 to 400 mV, and the dual output voltage ranges are 1 to 1.6 V and 2 to 4.6 V for $V_{{BOOST}}$ and $V_{{OUT}}$ , respectively. [ABSTRACT FROM AUTHOR]

Based on a general critical condition of subharmonic oscillation in terms of the loop gain, many closed-form critical conditions for various control schemes in terms of converter parameters are derived. Some previously known critical conditions become special cases in the generalized framework. Given an arbitrary control scheme, a systematic procedure is proposed to derive the critical condition for that control scheme. Different control schemes share similar forms of critical conditions. For example, both V^2 control and proportional voltage mode control have the same form of critical condition. A peculiar phenomenon in average current mode control where subharmonic oscillation occurs in a window value of pole can be explained by the derived critical condition. A ripple amplitude index to predict subharmonic oscillation proposed in the past research has limited application and is shown invalid for a converter with a large pole comparable to the switching frequency. [ABSTRACT FROM PUBLISHER]

The cyclically switching operation of a novel zero-voltage-zero-current-switching three-level converter is briefly presented. Based on a steady-state time-domain analysis of each equivalent switching topology, an average model is obtained. Small-signal open-loop ac line-to-output, control-to- output, and output-current-to-output-voltage transfer functions are deducted. The stability, gain margin, and phase margin of the open-loop transfer functions are studied. After designing the closed loop, the study of the audiosusceptibility and closed-loop output impedance allows for a dynamic analysis: the transient responses to changes in the input voltage and load current are obtained. The results got from the small-signal modeling are compared and confirmed by those obtained by PSPICE simulation and those measured in the laboratory, on an experimental converter of 4.5 kW. [ABSTRACT FROM AUTHOR]

With reference to a recently published paper, the realization of line and load regulation in switched-capacitor-based converters is discussed. We point out that achieving zero-current switching at the expense of losing line and load regulation is not practically feasible. [ABSTRACT FROM AUTHOR]

In this letter, it is verified that the main result of the above article on converging the voltage tracking error of a buck converter controlled by a fractional-order sliding mode controller cannot be logically justified. The root cause of this inconsistency, which is an improper use of an inequality, is discussed. [ABSTRACT FROM AUTHOR]

The all-pass filter method is proposed to approximately realize time-delayed chaotic electronic circuits. The amplitude-frequency characteristic and group time delay of the all-pass filter are analyzed and compared with the known low-pass filter. The number of filters in cascade is evaluated. Using the all-pass filter method, the infinite-dimensional time-delayed nonlinear system is reduced to finite-dimensional ordinary differential equations. The corresponding time-delayed chaotic electric circuits with all-pass filters are constructed, which are experimentally proven to be effective in the range of precision. The obtained experimental results well confirm the theoretical and numerical results. The proposed method is specifically suitable for the implementation of chaotic circuits with long time delay. [ABSTRACT FROM AUTHOR]

Digital filters in cascade form enjoy many advantages over their equivalent single-stage realizations in that lower coefficient sensitivity, higher throughput, reduced computational and smaller implementation cost can be achieved. However, the numerical design and optimization of such structure are of much more difficulty than the single-stage case if the filter coefficients are restricted to be of discrete values. This is mainly due to the non-convexity of the constraints, which rules out the possibility of employing sophisticated convex optimization techniques as well as the guaranteed global optimality. In this work, a general-purpose algorithm is proposed for the design of linear phase finite impulse response (FIR) filters in cascade form with discrete coefficients. The proposed algorithm decomposes the overall filter into subfilters during the traverse of a tree search of the overall filter. Discrete-valued linear phase FIR filters are able to be searched and decomposed into both symmetric and non-symmetric subfilters. The optimization complexity is of the same order as the single-stage filter optimization. Design examples have shown that the proposed algorithm is capable of achieving notable reduction in both implementation cost and adder depth compared with their single-stage optimum designs. [ABSTRACT FROM PUBLISHER]

A dual modulation technique to improve power conversion efficiency with minimal increase in output voltage ripple is presented. The worsening switching noise caused by parasitic resistance and inductance due to high-switching operation can also be alleviated by the proposed ac ripple detector. Furthermore, the dual modulation method can speed up the load transient response since the switching frequency can increase to 5 MHz during the transient period. At very light loads, the switching frequency is always kept higher than the acoustic frequency to avoid noisy sound. Experiment results show that the converter operates at 5 MHz using a small inductor of 1 \mu \H. The load transient response time is shorter than 3 \mu \s when load current changes from 150 to 450 mA or vice versa. Power efficiency is kept higher than 85% over a wide load current range. Specifically, light efficiency can be raised to about 45% above that of the conventional design. [ABSTRACT FROM PUBLISHER]

A 5.0-GHz-band monolithic direct-conversion receiver front end employing subharmonic mixers (SHMs) is demonstrated in 0.18-/μm CMOS technology. Instead of using transistors as transconductors, the SHMs adopt on-chip 1:4 transformers to achieve voltage gain, and hence, excellent local-oscillator self-mixing suppression and good linearity can be obtained. Additionally, a CMOS-compatible postprocess is used to selectively remove the silicon substrate underneath the inductors and transformers of the receiver front end. While dissipating 43.9 mW from a 1.8-V supply, the micromachined receiver front end exhibits a voltage gain of 28.0 dB, a noise figure of 9.7 dB, a third-order input intercept point of -7.8 dBm at 5.0 GHz, and an input-referred dc offset of -118.0 dBm. The proposed receiver front end is further integrated with analog baseband circuits, a fractional-N frequency synthesizer, and a serial-to-parallel data converter to accomplish a multioperation-mode receiver. [ABSTRACT FROM AUTHOR]

By means of components placement, the buck-boost and diagonal half-bridge forward converters are combined to create a novel single-stage high power factor correction (HPFC) diagonal half-bridge forward converter. When both the PFC cell and dc-dc cell operate in DCM, the proposed converter can achieve HPFC and lower voltage stress of the bulk capacitor. The circuit analysis of the proposed converter operating in DCM + DCM mode is presented. In order to design controllers for the output voltage regulation, the ac small-signal model of the proposed converter is derived by the averaging method. Based on the derived model, the proportional integral (PI) controller and minor-loop controller are then designed. The simulation and experimental results show that the proposed converter with the minor-loop controller has faster output voltage regulation than that with the PI controller despite the variations of line voltage and load. Finally, a 100-W prototype of the proposed ac-dc converter is implemented and the theoretical result is experimentally verified. [ABSTRACT FROM AUTHOR]

Differential flatness of buck, buck-boost, and boost converter models is shown. Its benefits if used for controlling the output voltage of these converters are revealed by comparing the flatness-based control with passivity-based and linear control. Two observers for the boost converter are suggested one of which requires only the measurement of the converters output voltage. Both observers can be used with minor changes for the buck-boost converter. Two flatness-based online trajectory planning algorithms are suggested. They exploit the parametrization of the trajectories in the energy. One of them is designed to achieve fast setpoint transitions during converter start-up or despite sudden load steps while simultaneously respecting the converters physical constraints. The other one is considered for applications in power factor correction. Different stabilization strategies are compared. The viability of the observers, the algorithm, and the stabilization strategies are verified by simulations of switched nonideal converter models. [ABSTRACT FROM AUTHOR]

The concept of loss-free complex impedance network elements (i.e., elements with active and reactive impedance components and yet loss-free) is introduced. Synthesis of such elements by means of switched-mode power converters with appropriate control has been demonstrated to be possible. Some possible power processing-related applications of these elements are indicated, such as improved matching between ac sources and loads and VAR compensation. It has further been demonstrated that loss-free complex impedance elements are suitable for modeling many power processing systems for the purpose of analysis as well as for design purposes. [ABSTRACT FROM AUTHOR]

This study addresses a grid-connected photovoltaic (PV) generation system. In order to make the PV generation system more flexible and expandable, the backstage power circuit is composed of a high step-up converter and a pulsewidth-modulation (PWM) inverter. In the dc-dc power conversion, the high step-up converter is introduced to improve the conversion efficiency of conventional boost converters and to allow the parallel operation of low-voltage PV modules. Moreover, an adaptive total sliding-mode control system is designed for the current control of the PWM inverter to maintain the output current with a higher power factor and less variation under load changes. In addition, an adaptive step-perturbation method is proposed to achieve the objective of maximum power point tracking, and an active sun tracking scheme without any light sensors is investigated to make PV plates face the sun directly in order to capture maximum irradiation and enhance system efficiency. Experimental results are given to verify the validity of the high step-up converter, the PWM inverter control, the ASP method, and the active sun tracker for a grid-connected PV generation system. [ABSTRACT FROM AUTHOR]