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This paper investigates the fixed-time stabilization problem for a class of nonlinear systems via event-triggered control. The event-triggered mechanism can be applied to the nonlinear system with the coexistence of low-order and high-order nonlinearities. In order to deal with these low-order and high-order terms as well as achieve the objective of fixed-time stabilization, the initial value of the system is divided into two cases, and then the event-triggered controller is designed, respectively. By switching control theory, it is proved that the nonlinear system is globally fixed-time stable under the designed controller and the Zeno behavior can be excluded. Finally, two simulations show that the proposed technology is effective. [ABSTRACT FROM AUTHOR]

This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states. [ABSTRACT FROM PUBLISHER]

The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions are given for these concepts in engineering literature. After many years of their usage, F. Gardner in the 2nd edition of his well-known work, Phaselock Techniques, wrote “There is no natural way to define exactly any unique lock-in frequency” and “despite its vague reality, lock-in range is a useful concept.” Recently these observations have led to the following advice given in a handbook on synchronization and communications: “We recommend that you check these definitions carefully before using them.” In this survey an attempt is made to discuss and fill some of the gaps identified between mathematical control theory, the theory of dynamical systems and the engineering practice of phase-locked loops. It is shown that, from a mathematical point of view, in some cases the hold-in and pull-in “ranges” may not be the intervals of values but a union of intervals and thus their widely used definitions require clarification. Rigorous mathematical definitions for the hold-in, pull-in, and lock-in ranges are given. An effective solution for the problem on the unique definition of the lock-in frequency, posed by Gardner, is suggested. [ABSTRACT FROM AUTHOR]

This paper introduces a discrete wheel-switching chaotic system (DWSCS). Changing the controlling sequence of the wheel switch allows DWSCS to generate a large number of new chaotic sequences from a set of existing chaotic maps (seed maps). Simulations and analysis demonstrate the DWSCS's characteristics and chaotic behaviors. An FPGA design of DWSCS shows its effectiveness in hardware implementation. We also propose a pseudo-random number generator using DWSCS whose excellent performance has been shown in experiments and comparisons. [ABSTRACT FROM AUTHOR]

The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates allow the synthesis and implementation of any MVL digital circuit. The main drawback of this approach is the lack of existing integrated circuits that implement the universal set of MVL gates. This paper deals with: 1) the design and implementation of a universal set of IC gates, CMOS 0.35 µm technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer and latch memory circuits, based on the IC MVL gates, to illustrate the utilization of the proposed IC MVL gates for quaternary MVL. Implemented circuits demonstrate correct functionality of the implemented gates and feasibility of the MVL combinatorial and memory circuit design. The proposed gates allow designing MVL digital circuit taking advantage of the knowledge coming from the binary circuits. By using a methodology based on the boolean algebra, digital circuits designers can take advantage of it to decrease the design learn curve. [ABSTRACT FROM PUBLISHER]

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 \mum CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. [ABSTRACT FROM AUTHOR]

This paper aims at further investigating the finite-time distributed tracking control problems for multi-agent systems with a virtual leader under the conditions of fixed and switching topologies, respectively. Two continuous distributed tracking protocols are designed for tracking the virtual leader in finite time. Compared with the traditional distributed tracking protocols, the proposed distributed tracking protocols can reach consensus in finite time. In particular, to eliminate the chattering phenomenon occurred in non-Lipschitz dynamical systems, this paper introduces a saturation function to replace the original sign function in the proposed distributed tracking protocols. The improved protocols can guide all agents to track the virtual leader without chattering phenomenon in finite time for the same position. Numerical simulations are also given to validate the proposed distributed tracking protocols. [ABSTRACT FROM AUTHOR]

This paper proposes a dimensionless approach to analyze the multi-parametric stability behavior of switching converters, which can be characterized by a nonlinear time-periodic (NTP) system. The main objective is to analyze how multiple circuit parameters affect the stability patterns of the derived NTP system and to simplify the parametric complexity of such NTP system. In contrast to previous work, the proposed method focuses on the parametric resultant relationships of the NTP system in the sense of topological equivalence, and investigates its stability in terms of the homeomorphic NTP system. Firstly, an equivalent stability theory of NTP systems is proposed. Then, based on the equivalent theory, a normalized map is introduced and various interesting properties are derived so as to formulate the dimensionless approach. Moreover, the approximate solution of the NTP system in dimensionless parameter space is calculated by using the Galerkin method, and its stability pattern is identified with the help of eigenvalue analysis approach. Finally, a case study of one-cycle controlled Zeta PFC converter is discussed in detail to exemplify the application of the proposed method. These analytical results agree well with those ones obtained from experimental measurements. [ABSTRACT FROM AUTHOR]

Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of ~ 4 μW with 6 MHz at 0.5 V, which is 30% better than the counterpart design. [ABSTRACT FROM PUBLISHER]

This paper introduces a push-pull class-EM power amplifier for achieving low harmonic contents and high output power. By applying the push-pull configuration of the class-EM power amplifier, the proposed amplifier achieves an extremely lower total harmonic distortion (THD) and about four times higher output power than the conventional single class-EM power amplifier. Design curves of the proposed amplifiers for satisfying the class-EM ZVS/ZDVS/ZCS/ZDCS conditions are given. A design example is shown along with the PSpice-simulation and experimental waveforms for 1-MHz amplifier, considering the MOSFET drain-to-source nonlinear parasitic capacitances, MOSFET switch-on resistances, and equivalent series resistance of the inductors. The waveforms from the PSpice simulation and circuit experiment satisfied all the switching conditions, which has shown the accuracy of the design curves given in this paper and validated the effectiveness of the push-pull class-EM power amplifier. [ABSTRACT FROM PUBLISHER]

Switched dynamical systems can be found in many practical electronic circuits, such as various kinds of power converters, chaos generators, etc. This paper is concerned with the filter design problem for a class of switched system with average dwell time switching. Mode-dependent full-order filters are designed taking a more practical phenomenon, the asynchronous switching into account, where “asynchronous” means that the switching of the filters to be designed has a lag to the switching of the system modes. New results on the stability and l2-gain analyses for the systems are first given where the Lyapunov-like functions during the running time of subsystems are allowed to increase. In light of the proposed Lyapunov-like functions, the desired mode-dependent filters can be designed in that the unmatched filters are allowed to perform in the interval of the asynchronous switching before the matched ones are applied. In H\infty sense, the problem of asynchronous filtering for the underlying systems in linear cases is formulated and the conditions of the existence of admissible asynchronous filters are obtained. Two examples are provided to show the potential of the developed results. [ABSTRACT FROM PUBLISHER]

Charge balance analysis and state transition analysis are presented in analyzing hysteretic voltage mode switching converters working in the steady state. It is shown that the ideal buck converter with a current-sink load can only work in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM), and the same converter with a resistive load can work in CCM, but the output voltage ripple is very large compared to the hysteresis window. Previously published CCM designs are functional because their operations actually rely on the small but nonzero equivalent series resistance (ESR) of the filtering capacitor. For the CCM buck converter with nonzero ESR, our proposed state transition analysis gives a much more accurate switching frequency than previous approaches. The hysteretic voltage mode boost and buck-boost converters are then analyzed, and shown to have no feasible operating region. Crucial simulation results are presented to confirm the analyses. [ABSTRACT FROM PUBLISHER]

This paper studies linear passive electrical networks with ideal switches. We employ the so-called linear switched systems framework in which these circuits can be analyzed for any given switch configuration. After providing a complete characterization of admissible inputs and consistent initial states with respect to a switch configuration, the paper introduces a new state reinitialization rule that is based on energy minimization at the time of switching. This new rule is proven to be equivalent to the classical methods of Laplace transform and charge/flux conservation principle. Also we illustrate the new rule on typical examples that have been treated in the literature. [ABSTRACT FROM PUBLISHER]

We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated switched-capacitor power converter for self-powered wireless sensor nodes. The design features an efficient step-down charge-pump power stage and a frequency-programmable digital feedback controller. The subthreshold-region design significantly reduces the power dissipation in the controller. Meanwhile, the programmable switching-frequency digital-pulse-width-modulation control keeps the converter stay at high efficiency, without causing a random noise spectrum. Monolithic implementation effectively suppresses noise and glitches caused by parasitic components due to bonding, packaging, and PCB wiring. Design strategy, system modeling, optimization, and circuit implementation are addressed. An IC prototype was fabricated with a standard 0.35-μm digital CMOS n-well process. It precisely provides a dynamic- voltage-scaling-compatible adjustable power output from 0.8 to 1.5 V and from 400 μW to 7.5 mW. The switching frequency is programmable from 200 kHz to 1 MHz. It achieves 66.7% efficiency with a controller power dissipation of only 147.5 μW. [ABSTRACT FROM AUTHOR]

In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100×. [ABSTRACT FROM AUTHOR]

In this paper, a study of the operation of switched continuous-time filters (SCTFs), defined as continuous-time filters with elements that are alternatively switched on and off in the signal path, is conducted. A well-known example is the use of switched resistors to multiply their value, but the universe of applications is wider. First, a detailed calculation of the output of an SCTF in the frequency domain, which allows the examination of any SCTF in a general framework, is presented. This result particularly explains the resistor multiplication effect. Three application examples using switched elements are presented and examined as SCTFs: a nonideal sample & hold, a switched active filter that is tuned by varying the duty cycle of the switching, and a switched Gm-C filter to implement a chopper amplifier. In all cases, the theoretical background allows the examination of circuit behavior and limitations, and the analysis is supported by measurements or transient simulations. [ABSTRACT FROM AUTHOR]

A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: "step-down" and "step-up." These blocks are inserted in classical converters: buck, boost, buck-boost, Ćuk, Zeta, Sepic. The "step-down" C- or L-switching structures can be combined with the buck, buck-boost, Ćuk, Zeta, Sepic converters in order to get a step-down function. When the, active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The "step-up" C- or L-switching structures are combined with the boost, buck-boost, Ćuk, Zeta, Sepic converters, to get a step-up function. The steady-state analysis of the new hybrid converters allows for determing their dc line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (dc gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-voltage switching (ZVS) buck converter with a tapped inductor (TI) is proposed. This converter improves the conventional tapped inductor critical conduction mode buck converters that have the ZVS operation range determined by the TI turn ratios. It includes another soft switching range extension method, the current injection method, which gives an additional design freedom for the selection of the turn-ratios and enables the optimal design of the winding ratio of the TI so that the efficiency may be maximized. This soft-switching buck converter is suitable for wide input range step-down applications. The principle of the proposed scheme, analysis of the operation, and design guidelines are included. Experimental results of the 100-W prototype dc-dc converter are given for hardware verification also. Finally, based on the proposed soft-switching technique, a new soft-switching topology family is derived. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of designing time-varying delay feedback controllers for master-slave synchronization of Lur'e systems. Two cases of time-varying delays are fully considered; one is the time-varying delay being continuous uniformly bounded while the other is the time-varying delay being differentiable uniformly bounded with the derivative of the delay bounded by a constant. Based on Lyapunov-Krasovskii functional approach, some delay-dependent synchronization criteria are first obtained and formulated in the form of linear matrix inequalities (LMIs). The relationship between synchronization criteria for the two cases of time-varying delays is built. Then, sufficient conditions on the existence of a time-varying delay feedback controller are derived by employing these newly-obtained synchronization criteria. The controller gains can be achieved by solving a set of LMIs. Finally, Chua's circuit is used to illustrate the effectiveness of the design method. [ABSTRACT FROM AUTHOR]

This paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering the threshold voltage of its devices. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst case coupling capacitance. Two implementations of this bus architecture are proposed, the alternate-Vt and the alternate forward body biased schemes, and are compared to a conventional bus scheme. For a flop distance of 1800 μm, the proposed schemes use the gained delay slack to reduce the total device width, and thus reducing the energy dissipation by 31.2%. For a 500-ps cycle time, the proposed bus schemes increase the maximum distance between flip-flops by 33%. [ABSTRACT FROM AUTHOR]

This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation. [ABSTRACT FROM AUTHOR]

This paper considers the problem of state estimation for discrete-time systems whose dynamics randomly switches between two linear stochastic behaviors (bimodal systems). The novelty of this paper is that no statistical information on the switching process is assumed available for the filter design. Two different approaches are here proposed to solve the estimation problem in these conditions. One method is based on a combined use of stochastic singular systems and of the minimax filtering theory, while the other relies on the maximum entropy principle. Based on these approaches two filtering algorithms are derived, whose features are theoretically and numerically compared. Some attention has been devoted to the study of the asymptotic properties of both the filters. [ABSTRACT FROM AUTHOR]

We consider a switching system composed of a finite number of linear delay differential equations (DDEs). It has been shown that the stability of a switching system composed of a finite number of linear ordinary differential equations (ODEs) may be achieved by using a common Lyapunov function method switching rule. We modify this switching rule for ODE systems to a common Lyapunov functional method switching rule for DDE systems and show that it stabilizes our model. Our result uses a Riccati-type Lyapunov functional under a condition on the time delay. [ABSTRACT FROM AUTHOR]

This paper describes the modeling of power-factor-correction converters under average-current-mode control, which are widely used in switch-mode power supply applications. The objective is to identify stability boundaries in terms of major circuit parameters for facilitating design of such converters. The approach employs a double averaging procedure, which first applies the usual averaging over the switching period and subsequently applies generalized averaging over the mains period. The resulting model, after two averaging steps and application of a harmonic balance procedure, is nonlinear and capable of describing the low-frequency nonlinear dynamics of the system. The parameter ranges within which stable operation is guaranteed can be accurately and easily found using this model. Experimental measurements are provided for verification of the analytical results. [ABSTRACT FROM AUTHOR]

With reference to a recently published paper, the realization of line and load regulation in switched-capacitor-based converters is discussed. We point out that achieving zero-current switching at the expense of losing line and load regulation is not practically feasible. [ABSTRACT FROM AUTHOR]