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This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the ${L}$ and ${K}$ least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining ${L}$ and ${K}$ variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with $L$ =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality. [ABSTRACT FROM AUTHOR]

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from $\mathbf {[{0,1}]}$ to $\mathbf {[-0.5,1]}$. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78% to 0.046%, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74% can achieve nearly $\mathbf {90\times }$ improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation. [ABSTRACT FROM AUTHOR]

Emerging advanced System-on-Chip (SoC) designs contain more and more complicated functions to be accelerated. This presents a challenge to conventional design approaches which use different hardware architectures or separate hardware accelerators to implement the various functions. To tackle this challenge, for the first time, we propose a generalized hardware accelerator called “Huicore” to speed up diverse functions on the same substrate. Through the analysis and transformation of mathematical characteristics, we reveal the commonality of many complicated functions using the CORDIC algorithm. Then we explore a reconfigurable architecture to implement them. The proposed reconfigurable accelerator can not only accelerate the implementation of many complicated functions, but also has small area, low power consumption and high precision. It is very suitable for integration in a SoC system to accelerate the implementation of various applications. [ABSTRACT FROM AUTHOR]

Recently, massive multiple-input multiple-output (MIMO) detection schemes based on message passing detection (MPD) have attracted extensive attention due to their good performance-complexity tradeoff. In this paper, to facilitate a high-throughput detector design, we introduce a layered updating schedule and propose an improved layered MPD (ILMPD) algorithm. In the new algorithm, several algorithmic transformations or approximations are derived for lower complexity. For instance, by exploiting the property of quadratic functions, the numbers of multiplications and additions in the constellation matching are both reduced by half; Through reasonable approximations, the multiplication, addition, and sorting operations in the initialization are all removed. Moreover, a lightweight early termination strategy is explored, reducing the number of detection iterations by nearly 20%. Based on the proposed ILMPD algorithm, an area-efficient architecture is devised, where several optimization methods are proposed for fewer resources and higher clock frequency. Compared with the state-of-the-art design, the presented ILMPD detector can deliver a nearly $3\times $ higher area efficiency. A reconfigurable version of the proposed detector has also been developed, which can well support modulations QPSK to 256-QAM and still exhibits a superior area efficiency. [ABSTRACT FROM AUTHOR]

Implementing finite impulse response (FIR) adaptive filters by employing the sums of signed-powers-of-two (SOPOT) arithmetic may lead to simpler hardware and consequently reduced power consumption. In this paper, one evaluates the effects of SOPOT arithmetic on the adaptive filter’s recursion algorithms. The filters’ coefficients and algorithms’ underlying variables are fully operated using SOPOT arithmetic in the whole iterative process. More specifically, one evaluates convergence rate, numerical stability, and accuracy since using few signed-powers-of-two (SPT) terms propagates numerical errors during the adaptive cycle that may impair the algorithm behavior. The SOPOT approximations are obtained through the technique known as Matching Pursuits with Generalized Bit-Plane (MPGBP) algorithm, with notable cost-performance trade-off and low computational complexity. Results are provided for the Least-Mean-Squares (LMS), the Normalized Least-Mean-Squares (NLMS) and the Recursive-Least-Squares (RLS) algorithms, considering adaptive filters employed for system identification and change detection. [ABSTRACT FROM AUTHOR]

The TICER (TIme-Constant Equilibration Reduction) algorithm is a well-known resistor-capacitor (RC) network reduction algorithm. It finds wide applications in integrated circuit post-layout simulation tools. However, the original algorithm is one-dimensional in that each step eliminates one circuit node to obtain an approximately equivalent circuit by connecting additional elements to the neighboring nodes after each elimination. This work extends the TICER algorithm to its high-dimensional version in the sense that each step eliminates a subcircuit as a whole to obtain an approximately equivalent circuit, again by connecting extra elements to the neighboring nodes after each elimination. In practice the high-dimensional TICER (HD-TICER) algorithm finds many advantages over the classical one-dimensional TICER (1D-TICER) algorithm, which is a special case of the HD-TICER algorithm. An elegant mathematical derivation of the HD-TICER algorithm is provided by applying the notion of driving point impedance (DPI). The advantages of the HD-TICER algorithm are demonstrated by application to reductions of some purely resistive networks and RC networks. An approximate time constant estimation method is also provided for selection of a subblock circuit to eliminate. [ABSTRACT FROM AUTHOR]

Deep Neural Networks (DNNs) are increasingly being used in a variety of applications. However, DNNs have huge computational and memory requirements. One way to reduce these requirements is to sparsify DNNs by using smoothed LASSO (Least Absolute Shrinkage and Selection Operator) functions. In this paper, we show that irrespective of error profile, the sparsity values obtained using various smoothed LASSO functions are similar, provided the maximum error of these functions with respect to the LASSO function is the same. We also propose a layer-wise DNN pruning algorithm, where the layers are pruned based on their individual allocated accuracy loss budget, determined by estimates of the reduction in number of multiply-accumulate operations (in convolutional layers) and weights (in fully connected layers). Further, the structured LASSO variants in both convolutional and fully connected layers are explored within the smoothed LASSO framework and the tradeoffs involved are discussed. The efficacy of proposed algorithm in enhancing the sparsity within the allowed degradation in DNN accuracy and results obtained on structured LASSO variants are shown on MNIST, SVHN, CIFAR-10, and Imagenette datasets and on larger networks such as ResNet-50 and Mobilenet. [ABSTRACT FROM AUTHOR]

We present an approximate logarithmic multiplier with two-stage operand trimming, which prioritises area and energy consumption while retains acceptable accuracy. The multiplier trims the least significant parts of input operands in the first stage and the mantissas of the obtained operands’ approximations in the second stage. We evaluated the multiplier’s efficiency in terms of error, energy, and area utilisation using NanGate 45nm. The experimental results show that the proposed multiplier exhibits smaller area utilisation and energy consumption than the state-of-the-art designs and that it behaves well in image processing and image classification with convolutional neural networks. [ABSTRACT FROM AUTHOR]

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design. [ABSTRACT FROM AUTHOR]

State-of-the-art approaches that perform root computations based on the COordinate Rotation Digital Computer (CORDIC) algorithm suffer from high latency in performing multiple iterations. Therefore, root computations based on the CORDIC algorithm cannot meet the strict latency requirements of some applications. In this paper, we propose a methodology for performing ${N}$ th root computations on floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method divides an ${N}$ th root computation into several subtasks approximated by the PWL algorithm. It determines the widest segments of the subtasks and the smallest fractional width needed to satisfy the predefined maximum relative error $Max\_{}Err_{r}$. Our design is coded in Verilog HDL and synthesized under TSMC 40 nm CMOS technology. The synthesized results show that our design can reach the highest frequency of 2.703 GHz with an area consumption of $2608.84~\mu ~\text{m}^{2}$ and a power consumption of 2.4476 mW. Compared with one state-of-the-art architecture, our design saves 91.60%, 89.84%, and 63.33% of the area, power, and latency @1.89GHz frequency, respectively, while reducing $Max\_{}Err_{r}$ by 57.30%. In addition, it saves 94.52%, 92.68%, and 73.17% of the area, power, and delay @1.89GHz frequency, respectively, and reduces $Max\_{}Err_{r}$ by 1.65% when compared with the other state-of-the-art design. [ABSTRACT FROM AUTHOR]

We present a method to emulate a leaky integrate-and-fire (LIF) model in a field-programmable gate array (FPGA) in a hardware-efficient manner. The simplified spike-response model (SRM0) is chosen as an LIF model. For the hardware-efficient implementation of SRM0, we adopt the template-scaling-based exponential function approximation (TS-EFA). This method allows high precision and low latency exponential function approximations with the efficient use of hardware resources. We subsequently propose an algorithm for SRM0, which leverages the advantage of TS-EFA. An implementation of 512 neurons conforming to SRM0 in an FPGA highlights (i) high precision of SRM0 emulation (mean squared error of membrane potential approximation: $4\times 10^{-12} - 1\times 10^{-10}$), (ii) low latency (eight clock cycles), and (iii) high efficiency in hardware usage (only 125b memory per neuron). [ABSTRACT FROM AUTHOR]

Aiming at reducing the complexity of minimum mean square error (MMSE) detection in massive multiple-input multiple-output (MIMO) systems, this paper proposes a detection algorithm with high convergence rate and an efficient hardware architecture based on second-order Richardson iteration (SORI). In the proposed algorithm, a pre-iteration-based initialization method is presented to accelerate the convergence without extra complexity. In addition, the approximation of relaxation factor and the log-likelihood ratio (LLR) is introduced to further reduce computing load. Theoretical analysis demonstrates the advantages of the proposed algorithm in fast convergence and low complexity, and simulation results show that the proposed algorithm can efficiently approach MMSE performance. Based on this algorithm, a flexible hardware architecture is designed, which is deeply pipelined to support $128\times U$ ($8\leq U\leq 32$) massive MIMO detection with the configurable number of iterations, and a folded dual-mode systolic array (DMSA) is fully utilized to achieve the flexibility with low hardware consumption. Implemented on Xilinx Virtex-7 FPGA and SMIC 40nm CMOS technology, the proposed detector is competitive in terms of energy and area efficiency compared to state-of-the-art iterative detectors, and it can adapt to the varied channel condition and the number of users in massive MIMO systems. [ABSTRACT FROM AUTHOR]

This paper addresses a general method for parameter identification in distributed parameter systems (DPSs) based on a reference model and measurement information. Moreover, the developed identification method is used to deal with secure communication problems. Firstly, in combination with the historical information measured by sensors, an iterative approach based on an approximator is put forward. Meanwhile, an execution scheme for the iterative approach is provided by an optimization policy. Subsequently, by bringing new mechanisms into quantum particle swarm optimization (QPSO) algorithm to enhance its search capability, we propose quantum-leading-following-based optimization (QLFBO) algorithm, which serves the optimization policy. Further, the global convergence for QLFBO algorithm is proved combined with the parameter identification problem of DPSs, and the computational complexity on this algorithm is discussed in detail. Finally, simulation experiments on the diffusion-reaction model are carried out by the iterative approach based on QLFBO algorithm under different measurement ways. Simultaneously, secure communication depending on this model is performed in the double-scroll Chua’s circuit and a lotus image via the investigated iterative strategy and encryption-decryption scheme. Simulation results verify the validity and practicability of the developed method. [ABSTRACT FROM AUTHOR]

In this paper, $H_\infty $ control problem is investigated by off-policy integral reinforcement learning (IRL) method for the nonlinear systems with completely unknown dynamics, disturbances, and constrained-input. Firstly, according to a model-based policy iteration (PI) algorithm, a model-free algorithm is proposed based on the derived iterative equation, and the equivalence of model-based PI algorithm and model-free algorithm is proven. Then, the model-free algorithm is implemented by off-policy IRL technology to solve the Hamilton-Jacobi-Isaacs (HJI) equation with the collected system data by the least-square approach, where three neural networks (NNs) are constructed to approximate the value function, control and the disturbance. Finally, our proposed methods are applied to stabilize an autonomous third-order Chua’s chaotic circuit system and a non-autonomous second-order memristive chaotic circuit system to illustrate the efficiency of the proposed method. [ABSTRACT FROM AUTHOR]

For adaptive echo cancellation in hands-free communication systems, a family of bias-compensated sparsity-aware normalized least mean M-estimate (NLMM) algorithms is proposed that are robust to both impulsive noise and noisy inputs. First, we define a new cost function that integrates the M-estimate function of the a posteriori error, the Riemannian distance between the current and previous weight vectors, and the $L_{0}$ norm of the weighted current weight vector. By minimizing the defined cost function, we develop the sparsity-aware NLMM algorithms to achieve robustness against the impulsive noise. Then, an improved cost function is developed and proved to be unbiased in the presence of input noise. This leads to the development of the bias-compensated sparsity-aware NLMM algorithms that can deal with noisy inputs. The stability and computational complexity of the proposed algorithms are analyzed as well. Experimental results for system identification and adaptive echo cancellation demonstrate that the proposed algorithms outperform the existing ones in terms of convergence rate and steady-state misalignment. [ABSTRACT FROM AUTHOR]

In this paper, we propose a hardware friendly On-Chip Training Algorithm for the memristive Neuromorphic circuits (OCTAN). Although the proposed algorithm has a simple hardware like that of the random weight change (RWC) algorithm, it is much more efficient in terms of convergence speed and accuracy. In this algorithm, weights of the circuit are updated individually by a small value and the effect of individual weight update is assessed. If the weight change causes an increase in the error of the network, the weight update is reversed by applying the same change in the reverse direction twice. The usefulness of the proposed algorithm is verified by training some neuromorphic circuits for different applications. Compared to RWC and stochastic least-mean-squares (SLMS) training algorithms, our proposed algorithm needs, on average, $329\times $ fewer epochs to find the minimum error point. Moreover, the accuracy of the networks trained by OCTAN is, on average, about 46% higher than those of RWC and SLMS algorithms. Additionally, a hardware for OCTAN is presented. This hardware provides a speedup of $172\times $ ($61\times $) compared to that of the RWC (SLMS) algorithm. Finally, the impact of PVT (process, voltage, and temperature) variations is studied on the proposed training hardware indicating an average training error increase of less than 3.27% in the presence of variations. [ABSTRACT FROM AUTHOR]

This paper presents different approximate designs for computing the FFT. The tradeoff between accuracy and performance is achieved by adjusting the word length in each computational stage. Two algorithms for word length modification under a specific error margin are proposed. The first algorithm targets an approximate FFT for an area-limited design compared to the conventional fixed design; the second algorithm targets performance so it achieves a higher operating frequency. Both of the proposed algorithms show that an efficient balance between hardware utilization and performance is possible at stage-level. The proposed approximate FFT designs are implemented on FPGA; experimental results show that hardware utilization using the first approximate algorithm are reduced by at least nearly 40%. The second algorithm increases performance of the designs by over 20%. Fine granularity design is also investigated, where the FPGA resources for a 256-point FFT computation can be further reduced by nearly 10% compared to a coarse design. Finally, the proposed approximate designs are applied to a feature extraction module in an isolated word recognition system; the numbers of LUTs and FFs for the Mel frequency cepstrum coefficients (MFCC) extraction module are decreased by up to 47.2% and 39.0%, respectively with a power reduction of up to 27.0% at a loss in accuracy of less than 2%. [ABSTRACT FROM AUTHOR]

High efficiency video coding (HEVC) uses large size of discrete cosine transforms (DCT), which increases hardware complexity quadratically. However, higher order DCTs are used less than 10% of the time and can tolerate some approximation without any noticeable degradation in the coding performance. Therefore, to reduce the computational complexity, an approximation algorithm is proposed in this paper. To achieve this, a new generalized model for the HEVC compliance DCT kernel is proposed using the Walsh Hadamard transform (WHT)-based matrix decomposition method. Thereafter, the proposed approximation algorithm replaces the rotation unit by a butterfly structure with minimum normality error. Four approximated architectures are implemented to provide different tradeoffs between coding accuracy and hardware complexity. Those architectures are less complex compared to the other architectures, and the coding performance is also better. The CMOS 90-nm ASIC implementation of the proposed 1-D DCT architecture requires 111.23k logic gates at 250-MHz operating frequency without any approximation. However, with the approximation algorithm, 43%–82% savings in the area-delay product are possible. When implemented on the Virtex-7 FPGA, the proposed approximated architecture reduces power consumption by 70% compared to that of the HEVC reference architecture to maintain a reasonable tradeoff between accuracy and complexity. [ABSTRACT FROM AUTHOR]

The approximate (multiplier-less) two-dimensional discrete cosine transform (DCT) is a widely adopted technique for image/video compression. This paper proposes a deterministic low-complexity approximate DCT technique that accurately configures the size of the transform matrix (${T}$) according to the number of retained coefficients in the zigzag scanning process. This is achieved by establishing the relationship between the number of retained coefficients and the number of rows of the ${T}$ matrix. The proposed technique referred to as the zigzag low-complexity approximate DCT (ZLCADCT), when compared with approximate DCT (ADCT), decreases the number of addition operations and the energy consumption while retaining the PSNR of the compressed image. In addition, the ZLCADCT eliminates the zigzag scanning process used in the ADCT. Moreover, to characterize the deterministic operation of the ZLCADCT, a detailed mathematical model is provided. A hardware platform based on FPGAs is then utilized to experimentally assess and compare the proposed technique; as modular, deterministic, low latency, and scalable, the proposed techniques can be implemented upon any change in the number of retaining coefficients by realizing only a partial reconfiguration of the FPGA resources for the additional required hardware. The extensive simulation and experimental results show the superior performance compared to previous ADCT techniques under different metrics. [ABSTRACT FROM AUTHOR]

In this paper, an exchange algorithm is proposed to design sparse linear phase finite impulse response (FIR) filters with reduced effective length. The sparse FIR filter design problem is formally an ${l} _{0}$ -norm minimization problem. This original design problem is re-formulated by encoding the filter coefficients using a binary encoding vector, which represents the locations of the zero and non-zero filter coefficients. An iterative 0-1 exchange process with proper direction control is proposed to propel the minimax approximation error toward the specified upper bound of error for sparsity maximization. The effective length is optimized with a lower priority than sparsity in the proposed algorithm. Simulation results show that the proposed algorithm is superior to the existing algorithms in terms of both sparsity and/or effective length in most cases. [ABSTRACT FROM AUTHOR]

The shooting method employed to compute the steady-state solution of circuits in the time domain is well known, largely used, and has been intensely studied in the literature. During these last decades, the large penetration of radio-frequency devices in the everyday activities has renewed some interest in this method, but the renewed interest is mainly focused on the simulation of large or very large circuits composed of thousands of transistors. The original formulation of the shooting method, despite being formally adequate, is unfeasible to handle this target. The introduction of iterative methods such as for example GMRES has largely pushed up the maximum size of the circuits that can be considered. Nevertheless, this may be not enough. We present an approach that faces the curse of dimensionality suffered by the original method. It allows both saving memory occupation and tackling circuits (or systems) with a number of differential and algebraic variables well above those managed by GMRES. Dimensionality is reduced by exploiting Galerkin projections. [ABSTRACT FROM AUTHOR]

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths using a 40-nm library. Comparison with previously presented approximated multipliers shows that the proposed circuits provide better power or speed for a target precision. Applications to image filtering and to adaptive least mean squares filtering are also presented in the paper. [ABSTRACT FROM AUTHOR]

Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world’s first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm2, while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users. [ABSTRACT FROM AUTHOR]

Reconstruction algorithms of compressively sampled data include solving a sparse approximation problem. This problem requires iterative search or optimization techniques. Software implementations are not fast enough for real-time applications of recovery algorithms and these algorithms should be implemented in hardware. This paper presents a low-complexity hardware for real-time reconstruction of compressively sensed signal using orthogonal matching pursuit algorithm. The main goal of this research is to provide a deterministic alternative to the random measurement matrix. The construction of this matrix is based on the connection between the parity check matrix of low-density parity-check (LDPC) codes and the measurement matrix of compressive sensing. For efficient hardware realization, a geometric approach to the construction of LDPC codes is used for matrix generation on the fly without requiring a lot of storage. Cyclic and binary structure of this matrix leads to the lower computational complexity and hardware cost in the reconstruction side. The described hardware has been implemented and evaluated on a virtex6 field-programmable gate array from Xilinx. Implementation results show that the proposed architecture has better performance in terms of hardware utilization. Moreover, the accuracy of the recovered signal is comparable with the previous works in which the random measurement matrix is used. [ABSTRACT FROM AUTHOR]

In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units. Compared with conventional LMs with exact units, the normalized mean error distance of 16-bit approximate LMs is decreased by up to 18% and the power-delay product has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate multipliers; it is found that the proposed approximate LMs are best suitable for applications allowing larger errors, but requiring lower energy consumption. Approximate Booth multipliers fit applications with less stringent power requirements, but also requiring smaller errors. Case studies for error-tolerant computing applications are provided. [ABSTRACT FROM AUTHOR]

In this paper, we propose model reduction algorithms based on the frequency-domain interval Gramians for 1-D and separable denominator 2-D discrete-time systems using balanced truncation as a parameterized combination of unweighted and the limited-frequency interval Gramians. The values of free parameters are computed using a line search optimization. The proposed algorithms provide a substantial improvement in the approximation error than the well-known existing techniques and generate stable reduced models along with an easily computable error-bound. The effectiveness of proposed algorithms is validated with the help of numerical examples of a sixth-order elliptic low-pass filter and a (6, 6)-order Roesser model of a separable denominator 2-D system. [ABSTRACT FROM AUTHOR]

We propose a progressive radiance estimation engine (PREE) hardware architecture to accelerate the processing of the progressive photon mapping with satisfactory graphic quality. The presented PREE architecture consists of four progressive radiance estimation units (PREUs), approximate full task schedule-oriented hit-point update operation controller (AFTSO-HpUOC) and approximate data-independent schedule-oriented radiance evaluation controller (ADISO-REC). The PREUs accelerate the radiance estimation computation by a pipeline technique and share and configure the hardware resource for hit-point update operation and radiance evaluation. Through AFTSO-HpUOC and ADISO-REC, the data can be efficiently dispatched to achieve better parallelism and the data dependence can be alleviated within the four PREUs, respectively. The core area of the proposed PREE architecture implemented in TSMC 90-nm CMOS process is 1.78 mm2. According to the post-layout simulation results, the implementation achieves 496.79 million hit-point update operations per second (MHpUO/s) and consumes 184 mW at 125 MHz for Cornell box with three balls. [ABSTRACT FROM AUTHOR]

Adaptive dynamic programming (ADP) is an effective algorithm that has been successfully deployed in various control tasks. For many emerging applications where power consumption is a major design consideration, the conventional way of implementing ADP as software executing on a general-purpose processor is not sufficient. This paper proposes a scalable and low-power hardware architecture for implementing one of the most popular forms of ADP called action-dependent heuristic dynamic programming. Different from most machine-learning accelerators that mainly focus on the inference operation, the proposed architecture is also designed for energy-efficient learning, considering the highly iterative and interactive nature of the ADP algorithm. In addition, a virtual update technique is proposed to speed up the computation and to improve the energy efficiency of the accelerators. Two design examples are presented to demonstrate the proposed algorithm and architecture. Compared with the software approach running on a general-purpose processor, the accelerator operating at 175 MHz achieves 270 times improvement in computational time while consuming merely 25 mW power. Furthermore, it is demonstrated that the proposed virtual update algorithm can effectively boost the energy efficiency of the accelerator. Improvements up to 1.64 times are observed in the benchmark tasks employed. [ABSTRACT FROM PUBLISHER]

This paper proposes a new optimization framework for the joint optimization of sparsity and filter order (JOSFO) for FIR filter design. Since the cost function for JOSFO involves \ell 0 and non-uniform overlapped group \ell 0 norms, which are not convex, a global optimal solution is difficult to obtain. To find an approximate solution of the non-convex problem, existing approaches repeat the following steps: 1) approximate the cost function; 2) find candidates of zero coefficients by minimizing the cost function; and 3) set them to zero. On the other hand, this paper directly solves the optimization problem, without any approximation to the cost function, by using the alternating direction method of multipliers with the pseudo-proximity operators of \ell 0 and non-uniform non-overlapped group \ell 0 norms. Experimental results show that resulting filters designed by the proposed method have sparser coefficients and lower orders, while satisfying filter specifications, such as an error from a desired frequency response. [ABSTRACT FROM PUBLISHER]

Channel estimation errors have a critical impact on the reliability of wireless communication systems. While virtually all existing wireless receivers separate channel estimation from data detection, it is well known that joint channel estimation and data detection (JED) significantly outperforms conventional methods at the cost of high computational complexity. In this paper, we propose a novel JED algorithm and corresponding VLSI designs for large single-input multiple-output (SIMO) wireless systems that use constant-modulus constellations. The proposed algorithm is referred to as PRojection Onto conveX hull (PrOX) and relies on biconvex relaxation (BCR), which enables us to efficiently compute an approximate solution of the maximum-likelihood JED problem. Since BCR solves a biconvex problem via alternating optimization, we provide a theoretical convergence analysis for PrOX. We design a scalable, high-throughput VLSI architecture that uses a linear array of processing elements to minimize hardware complexity. We develop corresponding field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, and we demonstrate that PrOX significantly outperforms the only other existing JED design in terms of throughput, hardware-efficiency, and energy-efficiency. [ABSTRACT FROM AUTHOR]

A Maximum Power Point Tracking (MPPT) circuit for a 0.7-W photovoltaic (PV) system is proposed. The circuit employs a modified hill-climbing algorithm based on a 3-points comparison instead of the traditional 2-points comparison. The adopted algorithm simplifies the detection of the Maximum Power Point (MPP) and enables the implementation of a periodic sleep-mode to reduce the overall power consumption without compromising effective tracking of irradiance variations. Moreover, to achieve high MPP tracking efficiency, a low-power linear analog multiplier is implemented to accurately compute the instantaneous power of the PV source from its sensed voltage and current levels. This power-metering function is realized in the analog domain to eliminate the need for data converters and to minimize the MPPT circuit's power consumption. A complete design of the proposed circuit is implemented in 0.18- \mu\textm BiCMOS process in less than 1.55 mm 2 and consumes less than 25 \mu\textW with the digital core running at 500 kHz and a measured peak MPP tracking efficiency of 99.7%. [ABSTRACT FROM PUBLISHER]

Polar codes are a recently discovered family of capacity-achieving error-correcting codes. Among the proposed decoding algorithms, successive-cancellation list decoding guarantees the best error-correction performance with codes of moderate lengths, but it yields low throughput. Speed-up techniques have been proposed in the past: most of them rely on approximations that degrade the error-correction capability of the algorithm. We propose a speed-up technique for successive-cancellation list decoding of polar codes that is exact for list size of 2, while its approximations bring negligible error-correction performance degradation (<0.05 dB) for other list sizes. A decoder architecture is designed: the proposed technique increases the throughput of a factor of $3.16\times $ , at the cost of 14.2% in area occupation. [ABSTRACT FROM PUBLISHER]

Compressed sensing (CS) allows a signal that is sparse in certain domain to be acquired and reconstructed accurately with only a small number of samples. In this paper, we propose an adaptive (\ell0,\ell1) complex approximate message passing (CAMP) algorithm and its hardware implementation for complex-valued sparse signal recovery. Compared with the existing CAMP algorithm which solves \ell1-regularized least squares problems, our proposed algorithm adaptively switches between \ell0 and \ell1-regularized least squares and therefore significantly outperforms the original CAMP. We implement the architecture in a medium-sized field-programmable gate array (FPGA) chip. For a sparse stepped frequency waveform radar application, we perform experiments on the simulated data and the data collected by a real radar system. According to the result, the decoder design achieves 7.2 dB improvement over the conventional CAMP architecture with less than 27.4% extra hardware cost. [ABSTRACT FROM PUBLISHER]

A family of algorithms based on a two-step Galerkin's method for approximating the solution of steady state problems formulated in the frequency domain are presented. Such methods work by reducing the number of unknowns of the conventional harmonic balance (hb) method. With respect to the state-of-the-art hb algorithm via gmres, the new algorithms lead to better convergence properties, reduced memory occupation and the ability to achieve acceptable approximations of the solution at reduced computational time. In this way the new approach allows analyzing circuits described by models that involve up to hundred thousands electrical unknowns. As a by-product, is it shown that the heuristic oversampling technique, which is largely used in hb commercial simulators, is here easily formalized as one step of the proposed methods and a profitable way to improve it is presented. [ABSTRACT FROM AUTHOR]

Graph-based heuristic for Multiple Constant Multiplication (MCM) has been an area of intensive research over the last two decades. To overcome the pitfalls of hidden partial sums and local minima inherent in trivial digraph formulation, this paper introduces an elementary digraph-to-hypergraph transformation to enable a new minimum arborescence (MA) formulation of MCM problem. Our proposed algorithm iteratively solves the MA problem from a strongly connected graph formed by adding new vertex from the least cost surviving hypergraph in the preceding iteration until no new vertex is found. As the visible and hidden edges of an elementary hypergraph (EHG) are interchangeable by swapping their values encoded in its hyperedge, previously removed vertex can be revived if it is a predecessor of the least cost surviving hyperedge as the hypergraph evolves. A by-product of this iterative algorithm is that its underlying EHG minimization can also be used for quality improvement of existing MCM solutions generated by other design algorithms or for engineering changes. Experimental results on benchmark filters show that our proposed algorithm can reduce their multiplier block areas by 2.9% to 14.9% and power consumptions by 2.8% to 20.1% over other advanced algorithms. A further $\sim$20% of area can be saved from the less area-efficient solutions of other design algorithms by the proposed EHG reoptimization. [ABSTRACT FROM AUTHOR]

Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length N could be derived from a pair of DCTs of length (N/2) at the cost of N additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, N>8. We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method. [ABSTRACT FROM AUTHOR]

A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 mm^2 and 16.10 mm^2 after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order. [ABSTRACT FROM AUTHOR]

Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology. [ABSTRACT FROM AUTHOR]

High-accuracy implementation of biological neural networks is a computationally expensive task, specially, for large-scale simulations of neuromorphic algorithms. This paper proposes a set of models for biological spiking neurons, which are efficiently implementable on digital platforms. Proposed models can reproduce different biological behaviors with a high precision. The proposed models are investigated, in terms of digital implementation feasibility and costs, targeting low-cost hardware implementation. Hardware synthesis and physical implementations on a field-programmable gate array show that the proposed models can produce biological behavior of different types of neurons with higher performance and considerably lower implementation costs compared with the original model. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm^2 QRD chip, fabricated in 0.13 \mum 1P8M CMOS technology, demonstrate that the proposed design for 4\,\times\,4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25^\circC. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency. [ABSTRACT FROM AUTHOR]

This paper proposes a novel constructive training algorithm for cascade neural networks. By reformulating the cascade neural network as a linear-in-the-parameters model, we use the orthogonal least squares (OLS) method to derive a novel objective function for training new hidden units. With this objective function, the sum of squared errors (SSE) of the network can be maximally reduced after each new hidden unit is added, thus leading to a network with less hidden units and better generalization performance. Furthermore, the proposed algorithm considers both the input weights training and output weights training in an integrated framework, which greatly simplifies the training of output weights. The effectiveness of the proposed algorithm is demonstrated by simulation results. [ABSTRACT FROM PUBLISHER]

An improved quasi-Newton (QN) algorithm that performs data-selective adaptation is proposed whereby the weight vector and the inverse of the input-signal autocorrelation matrix are updated only when the a priori error exceeds a prespecified error bound. The proposed algorithm also incorporates an improved estimator of the inverse of the autocorrelation matrix. With these modifications, the proposed QN algorithm takes significantly fewer updates to converge and yields a reduced steady-state misalignment relative to a known QN algorithm proposed recently. These features of the proposed QN algorithm are demonstrated through extensive simulations. Simulations also show that the proposed QN algorithm, like the known QN algorithm, is quite robust with respect to roundoff errors introduced in fixed-point implementations. [ABSTRACT FROM PUBLISHER]