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Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is based on quantified Boolean formulas (QBF) to detect multiple erroneous paths when taking into account the timing variations. We have proposed new gate-level timing variation and path slowdown models which enable us to formulate such a debugging problem as a QBF problem. The results on the ISCAS’85 and ISCAS’89 benchmarks show that our method enjoys on average 52.4% decrease in the size model, and 63.1% decrease in debugging time in comparison with existing methods. Moreover in situations where existing methods due to the size explosion of abundant copies cannot be applied, the proposed method detects erroneous gates in a reasonable runtime. [ABSTRACT FROM AUTHOR]

Dynamic flip-flop conversion (DFFC) is a time borrowing method for improving the performance of digital circuits. Existing types of DFFC [11], [12] suffer from successive critical and critical feedback paths that are frequently seen in digital circuits. Moreover, they are unable to increase the performance of the designs with short sequential depth. In this paper, we introduce a hybrid technique which utilizes DFFC together with a dynamic clock stretching mechanism. Our technique is able to mitigate the problems of successive critical and critical feedback path structures even in the presence of process variations. The results show that our hybrid technique is able to increase the performance of some ITC'99 and ISCAS'89 benchmarks by 24.4% on average while DFFC Type C increases the performance only by 8.4% on average. Furthermore, we have shown that our hybrid technique is able to tolerate process variations, 18% power supply variation, and 100 °C temperature variations, 27.3%, 16.4%, and 13.3% better than the state-of-the-art methods on average, respectively. [ABSTRACT FROM PUBLISHER]