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LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby encapsulating the design rules and process-specific structures. The templates can be located based on their relative positional information, which further enhances the description capability and portability. Interconnecting wires are routed on the grids for design rule abstractions, with additional customizations and support for multi-patterning. The functions for the on-grid placement and routing use advanced indexing and slicing with multi-dimensional object containers to improve the description and parameterization capabilities. Multiple TI-SAR ADC layouts are generated using LAYGO in 28–16 nm CMOS technologies. One instance is fabricated in a 16 nm CMOS FinFET process and measured, achieving a 38.2 dB signal-to-noise-and-distortion ratio (SNDR) at 7 GS/s after digital calibration and consuming 45.2 mW. Owing to its high customization capability, the design achieved the highest sampling rate (7 GS/s) among the generated ADCs. [ABSTRACT FROM AUTHOR]