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Keyword spotting (KWS) is a crucial function enabling the interaction with the many ubiquitous smart devices in our surroundings, either activating them through wake-word or directly as a human-computer interface. For many applications, KWS is the entry point for our interactions with the device and, thus, an always-on workload. Many smart devices are mobile and their battery lifetime is heavily impacted by continuously running services. KWS and similar always-on services are thus the focus when optimizing the overall power consumption. This work addresses KWS energy-efficiency on low-cost microcontroller units (MCUs). We combine analog binary feature extraction with binary neural networks. By replacing the digital preprocessing with the proposed analog front-end, we show that the energy required for data acquisition and preprocessing can be reduced by $29\times $ , cutting its share from a dominating 85% to a mere 16% of the overall energy consumption for our reference KWS application. Experimental evaluations on the Speech Commands Dataset show that the proposed system outperforms state-of-the-art accuracy and energy efficiency, respectively, by 1% and $4.3\times $ on a 10-class dataset while providing a compelling accuracy-energy trade-off including a 2% accuracy drop for a $71\times $ energy reduction. [ABSTRACT FROM AUTHOR]

Hyperdimensional computing (HDC) is a brain-inspired computing paradigm-based on high-dimensional holistic representations of vectors. It recently gained attention for embedded smart sensing due to its inherent error-resiliency and suitability to highly parallel hardware implementations. In this work, we propose a programmable all-digital CMOS implementation of a fully autonomous HDC accelerator for always-on classification in energy-constrained sensor nodes. By using energy-efficient standard cell memory (SCM), the design is easily cross-technology mappable. It achieves extremely low power, 5 $\mu \text{W}$ in typical applications, and an energy efficiency improvement over the state-of-the-art (SoA) digital architectures of up to $3\times $ in post-layout simulations for always-on wearable tasks such as Electromyography (EMG) hand gesture recognition. As part of the accelerator’s architecture, we introduce novel hardware-friendly embodiments of common HDC-algorithmic primitives, which results in $3.3\times $ technology scaled area reduction over the SoA, achieving the same accuracy levels in all examined targets. The proposed architecture also has a fully configurable datapath using microcode optimized for HDC stored on an integrated SCM-based configuration memory, making the design “general-purpose” in terms of HDC algorithm flexibility. This flexibility allows usage of the accelerator across novel HDC tasks, for instance, a newly designed HDC-algorithm for the task of ball bearing fault detection. [ABSTRACT FROM AUTHOR]

Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise, making aggressive voltage scaling attractive as a power-saving technique for both logic and SRAMs. In this work, we introduce the first fully programmable IoT end-node system-on-chip (SoC) capable of executing software-defined, hardware-accelerated BNNs at ultra-low voltage. Our SoC exploits a hybrid memory scheme where error-vulnerable SRAMs are complemented by reliable standard-cell memories to safely store critical data under aggressive voltage scaling. On a prototype in 22nm FDX technology, we demonstrate that both the logic and SRAM voltage can be dropped to 0.5V without any accuracy penalty on a BNN trained for the CIFAR-10 dataset, improving energy efficiency by 2.2X w.r.t. nominal conditions. Furthermore, we show that the supply voltage can be dropped to 0.42V (50% of nominal) while keeping more than 99% of the nominal accuracy (with a bit error rate ~1/1000). In this operating point, our prototype performs 4Gop/s (15.4 Inference/s on the CIFAR-10 dataset) by computing up to 13 binary ops per pJ, achieving 22.8 Inference/s/mW while keeping within a peak power envelope of 674uW – low enough to enable always-on operation in ultra-low power smart cameras, long-lifetime environmental sensors, and insect-sized pico-drones. [ABSTRACT FROM AUTHOR]

Broadband current sensors are key components in numerous applications, including power conversion, motor control, and smart-metering. We present a compressive sensing (CS) current sensor system-on-chip (SoC) designed and fabricated in STM 0.16 $\mu \text{m}$ Bipolar-CMOS-DMOS technology. The SoC is capable of measuring currents with amplitudes of up to 10 A peak with a sensing bandwidth of 1 MHz. Two broadband current sensing cores, each consisting of a Hall-effect probe, an AFE, and a 2 MS/s 9-bit ADC, are monolithically integrated together with a digital multi-mode compressive sensing encoder (DCSE) for data-rate reduction. We focus on the evaluation of CS as data compression codec for current sensing applications and on the details of the DCSE architecture designed for general purpose use. We introduce multi-block decoding that is a decoding modality to improve the reconstruction quality of “off-grid sparse” signals commonly occurring in practice. Moreover, we provide measurements of both the compression performance and power consumption of the SoC employed in two exemplary real-world applications; namely, sparse current sensing, and electrical appliance detection for non-intrusive load monitoring based on compressive measurements. [ABSTRACT FROM AUTHOR]

Duty-cycled low-rate Internet-of-things (IoT) sensors are employed in diverse applications, requiring configurable and energy-efficient on-chip and on-demand clock synthesis. We present an all-digital frequency-locked loop (AD-FLL) capable of generating an accurate clock selectively in stand-alone operation or locked to a 32kHz reference. We report measurement results of two prototypes in 65nm and 28nm CMOS offering a configurable clock multiplication factor of up to 32 786, resulting in a wide tuning-range from a few MHz to 2.4GHz and 1.6GHz, respectively. The challenges of slow start-up and deterministic jitter are addressed by a fast hybrid-mode start-up procedure and by various jitter reduction modes. We also introduce the concept of Transient Clocking that leverages the capabilities of the proposed AD-FLL to make a system operational after cold-start or wake-up before the supply voltage has stabilized. We study two application examples that highlight the versatility of the concept in IoT applications and show its potential to amortize the time and energy cost of typical system start-up tasks, like state-restoration or wake-up event classification. [ABSTRACT FROM PUBLISHER]

Near-sensor data analytics is a promising direction for internet-of-things endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data are stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a system-on-chip (SoC) based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65-nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep convolutional neural network (CNN) consuming 3.16pJ per equivalent reduced instruction set computer operation, local CNN-based face detection with secured remote recognition in 5.74pJ/op, and seizure detection with encrypted data collection from electroencephalogram within 12.7pJ/op. [ABSTRACT FROM PUBLISHER]

Compressive sensing (CS) is a signal acquisition strategy that, based on the assumption of sparsity, promises to relax the design constraints of signal acquisition systems with respect to conventional strategies. In this paper, we contrast signal acquisition systems for low-rate applications based on analog CS encoding with systems based on digital CS encoding. We consider the complete signal chain from acquisition to reconstruction, with particular attention to the effects of quantization, and show that the two schemes differ significantly in encoder precision, measurement resolution, compression ratio, and reconstruction quality. Further, we develop first-order power estimation models to asses the relative energy-efficiency of different CS and conventional signal acquisition systems. Our numerical evaluations suggest that when the power consumption of data storage/communication outweighs the power consumption of data acquisition and processing, analog CS systems can outperform their digital counterparts, despite their higher hardware complexity. Moreover, we provide evidence that the common special case of analog and digital encoding, known as non-uniform sampler, performs best under all conditions. [ABSTRACT FROM PUBLISHER]

In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5–14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 mm^2. Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices. [ABSTRACT FROM PUBLISHER]

In wireless sensor nodes with a tight power budget, minimizing both the amount of transmitted data and the complexity of the algorithms used for data compression are fundamental in achieving long battery life-time. Compressed Sensing (CS) has been proposed to process incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. We show that the architecture implementing parallel projection-based CS can be reused to realize a linear estimator able to minimize the transmitted data when the primary interest is the acquisition of a scalar feature of the signal rather than its entire profile. Further, we increase the energy-efficiency of the architecture by puncturing the sample stream which allows the duty-cycle of both the analog front-end and the analog-to-digital converter to be reduced. We found that conventional CS acquisition can be made more energy-efficient as it tolerates a certain amount of random puncturing, and also that more substantial power savings can be achieved when estimation is the target and undersampling is optimized by a suitable algorithm. In the latter case, the power consumption of all circuit blocks in the signal chain can be reduced by more than one order of magnitude with respect to the standard solution that samples and transmits raw data for off-board processing. The effectiveness of optimized undersampling is demonstrated in two case studies; first, the estimation of the amplitude of an electrical signal, and second, the estimation of the maximum solar radiation measured by a real-world sensor. [ABSTRACT FROM AUTHOR]

The thermal wall for many-core systems on-chip calls for advanced management techniques to maximize performance, while capping temperatures. Distributed and compact thermal models are a cornerstone for such techniques. System identification methodologies allow to extract models directly from the target device thermal response. Unfortunately, standard Auto-Regressive eXogenous models and Least Squares techniques cannot effectively tackle both model approximation and measurement noise typical of real systems. In this work, we propose a novel distributed identification strategy to derive distributed interacting thermal models. The presented method can cope with both process noise and temperature sensor noise affecting inputs and outputs of the adopted models. Online and offline versions are presented, and issues related to model order, sampling time and input stimuli are addressed. The proposed method is applied to the Intel's Single-chip-Cloud-Computer many-core prototype. [ABSTRACT FROM AUTHOR]

Lowering supply voltage is still the most effective technique to reduce dynamic power, and Vdd is being pushed toward the threshold voltage for ultra-low power applications. However, near-threshold circuit leakage power is comparable to the switching power and performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade off performance and power in a fine-grained manner. This style is fully compatible with state-of-the-art commercial physical design flows and imposes minimal area blow-up. It can be applied without any placement disruption on a fully placed design. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up to 45% while achieving more than 50% lower power as compared to single-Vdd implementations. [ABSTRACT FROM PUBLISHER]

The limited battery lifetime of modern embedded systems and mobile devices necessitates frequent battery recharging or replacement. Solar energy and small-size photovoltaic (PV) systems are attractive solutions to increase the autonomy of embedded and personal devices attempting to achieve perpetual operation. We present a batteryless solar-harvesting circuit that is tailored to the needs of low-power applications. The harvester performs maximum-power-point tracking of solar energy collection under nonstationary light conditions, with high efficiency and low energy cost exploiting miniaturized PV modules. We characterize the performance of the circuit by means of simulation and extensive testing under various charging and discharging conditions. Much attention has been given to identify the power losses of the different circuit components. Results show that our system can achieve low power consumption with increased efficiency and cheap implementation. We discuss how the scavenger improves upon state-of-the-art technology with a measured power consumption of less than 1 mW. We obtain increments of global efficiency up to 80%, diverging from ideality by less than 10%. Moreover, we analyze the behavior of supercapacitors. We find that the voltage across the supercapacitor may be an unreliable indicator for the stored energy under some circumstances, and this should be taken into account when energy management policies are used. [ABSTRACT FROM AUTHOR]

Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We propose a new reactivation solution that helps in controlling power supply fluctuations and achieving minimum reactivation times. Our structure limits the turn-on current below a given threshold through a sequential activation of the sleep transistors (STs), which are connected in parallel and sized using a novel optimal sizing algorithm. We also introduce a distributed physical implementation, which allows minimum layout disruption after ST insertion and minimizes routing congestion. [ABSTRACT FROM AUTHOR]