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This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear digital decoder (reconstruction filter) for incremental delta-sigma modulators. This decoder utilizes both the magnitude and pattern information of the modulator output to achieve accurate input estimation. Compared to the conventional linear filters with the same oversampling ratio (OSR), it can improve the converter’s signal-to-quantization noise ratio by a few dB to a few 10’s of dB with slight thermal noise performance degradation. Using the proposed decoder, the modulator’s OSR can be a few times less while achieving the same resolution and data rate, thus minimizing the modulator as well as its peripheral circuits’ energy consumption. In this paper, the proposed decoder is optimized for digital implementation, with its function being verified using a modulator prototype. This decoder is mainly designed for dc or near-dc signal conversions and it does not provide frequency notches. [ABSTRACT FROM AUTHOR]

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm2 and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of $3.23~\mu \text{m}^{2}$ (i.e. 764 ${F}^{2}$) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF’s uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips’ reliability under varied operating temperature from −40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by $1.16\sim 4.29\times $ , with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered. [ABSTRACT FROM AUTHOR]

Incremental analog-to-digital-converters (IADCs) are variants of $\triangle \Sigma $ ADCs, which have been increasingly used for low-power sensory applications in recent years. Most IADC applications require high resolution and high energy efficiency. In this paper, we present a systematic analysis of IADCs. We derive analytical design equations for practical IADC designs. Process limitations are included in the model as well. The equations are verified with a 14-bit second-order IADC design in a 0.18- $\mu \text{m}$ process. With the design equations, the theoretical energy efficiency bound is derived for IADCs. The efficiency bound is compared with previously reported IADC designs. It is found that the derived bound matches existing designs well. [ABSTRACT FROM AUTHOR]

This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a $\Sigma \Delta$ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard CMOS process. The total chip area of the digital decimation filter is only $4.5\times 145~\mu \text{m}^{2}$ per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 $\mu \text{W}$ under a typical 50-MHz clock frequency. [ABSTRACT FROM AUTHOR]

This paper presents a Class-AB audio power amplifier with state-of-the-art power efficiency and performance. In this work, the second stage transconductance of the three-stage power amplifier can be dynamically compensated, in order to automatically adjust the amplifier pole according to the operating condition of the output stage. Working with a current sensing module, the proposed dynamic transconductance compensation scheme is more power-efficient to allocate the frequency of non-dominant-pole under a specified stability requirement. A prototype chip is designed and fabricated using 55 nm CMOS process. The measured static current consumption of the core circuit is 0.35 mA with a 1.8 V supply voltage. −85 dB THD+N, 106 dB signal dynamic range and 55 mW output power are verified in silicon under a wide range of load capacitance from 5 pF to 20 nF. Measurement result shows the proposed transconductance compensation technique is effective in both constant voltage supply mode and dynamic supply (Class-G) mode. [ABSTRACT FROM AUTHOR]

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490\mum\times 7.4\mum and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18\mum technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit. [ABSTRACT FROM PUBLISHER]

We present an ultra-low power temperature sensor embedded in the passive RFID tag using the TSMC 1P6M 0.18 \mum standard CMOS process. Substrate parasitic NPN bipolar pair is exploited to generate the temperature dependent current signals for thermal sensing. A time-domain readout scheme which has high immunity to the on-chip resistor, capacitor and clock frequency process-voltage-temperature (PVT) spreads is further proposed. Measurement results of the embedded sensor within the tag system shows a sensing accuracy of \pm 1.5^\circ\ C (3\sigma) from -30^\circ\ C to 60^\circ\ C after one-point calibration at 20^\circ\ C, with a sensing resolution of 0.3^\circ\ C and a sampling rate of 68 samples per second. The embedded sensor draws 0.35 \muA from a 1 V supply at room temperature and occupies a chip area of 0.14 mm^2. [ABSTRACT FROM AUTHOR]

Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348\ \mum\times 7\ \mum. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 \mum technology shows that the DAC's figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise. [ABSTRACT FROM PUBLISHER]

This paper presents a CMOS single-chip gas recognition circuit, which encodes sensor array outputs into a unique sequence of spikes with the firing delay mapping the strength of the stimulation across the array. The proposed gas recognition circuit examines the generated spike pattern of relative excitations across the population of sensors and looks for a match within a library of 2-D spatio-temporal spike signatures. Each signature is drift insensitive, concentration invariant and is also a unique characteristic of the target gas. This VLSI friendly approach relies on a simple spatio-temporal code matching instead of existing computationally expensive pattern matching statistical techniques. In addition, it relies on a novel sensor calibration technique that does not require control or prior knowledge of the gas concentration. The proposed gas recognition circuit was implemented in a 0.35 \mu\ m CMOS process and characterized using an in-house fabricated 4 \times 4 tin oxide gas sensor array. Experimental results show a correct detection rate of 94.9% when the gas sensor array is exposed to propane, ethanol and carbon monoxide. [ABSTRACT FROM PUBLISHER]

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-μm CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology. [ABSTRACT FROM AUTHOR]