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This paper presents a digital readout integrated circuit (DROIC) for small pitch medium-wave infrared (MWIR) starring focal plane arrays (FPAs). To overcome the limited in-pixel resolution of such DROICs, the concept of error shaping is introduced in pulse frequency modulation (PFM)-based pixels. Multiple integration operations are performed in a single frame and the residue charge from each integration phase is retained and injected into the next charge packet. This over-integration routine provides a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. The concise structure of a PFM analog-to-digital converter (ADC) lends itself well to such an operation inside the pixel, while consuming low power. Along with a theoretical analysis of the technique, a prototype based on a $16\times 16$ array and sinc decimation filters is developed to demonstrate the performance of the proposed DROIC. With an in-pixel resolution of 5 bits and over-integration ratio (OIR) of 128, 395 noise electrons are demonstrated at full-well fill from the test array fabricated in a 90 nm bulk-CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a new self-calibration method for vector-sum phase shifters (PS) to compensate for process variations and achieve reconfigurable operating frequency. The calibration system generates a look-up table for the control voltages of the variable-gain amplifiers of the PS to minimize the rms phase error at a frequency of interest. The calibration system consists of a coupled-line coupler, an amplifier, a power detector (PD), an analog-to-digital converter, and a data processing unit. In this calibration method, first, the amplitudes of IQ vectors are swept and their powers are measured. Then, phase errors are calculated from these power measurements using the cosine formula. Finally, the vector pairs providing the least phase error are chosen for each desired phase shift. The practicality of the proposed system is demonstrated by realizing a self-calibrated $X$ -band 7-b PS fabricated in IHP 0.25- $\mu \text{m}$ SiGe BiCMOS technology, including the on-chip coupler, amplifier, and PD. The calibration system improves the rms phase error by at least 1°, does not degrade the rms gain error, and increases the insertion loss by 1.6 dB. The self-calibrated PS achieves a 2° rms phase error across $X$ -band frequencies. The overall chip size is 2.6 mm2. The power consumption of the PS and the overall system are 110 and 233 mW, respectively. This built-in calibration system mitigates process variation effects, and the performance of the PS can be optimized for any center frequency across $X$ -band. [ABSTRACT FROM AUTHOR]

This paper presents a wide range, voltage controlled-current source circuit that is optimized to compensate for both process and temperature variations. Compensation for process variations is realized by cancellation of the threshold voltage variations. Temperature compensation is applied by the use of a poly resistor. Ninety samples from 3 different chips of the same wafer run were measured, and for the nominal value of 25 nA, current sources have a standard deviation of 1.22% (4.8\times improvement over an uncompensated current reference). The simulated standard deviation is 8%, resulting a simulated improvement factor of 8\times, when samples from different wafer runs are to be measured. Measured temperature drift is 250 ppm/^\circC for a temperature range of 0–80 ^\circC. For the mentioned performance, the circuit consists of only 7 components occupying an area of 64 \mum\times\,91 \mum, using AMS 0.35 \mum, 5 V CMOS process technology. The new current source is used to mimic the behavior of an infrared detector, which creates current in the range of 1–50 nA. A modified version of proposed current source is also designed with no off-chip bias voltages, and has a temperature coefficient of 57 ppm/^\circC for 9 nA with an acceptable process compensation. [ABSTRACT FROM PUBLISHER]