Search

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep sub-micron MOS technologies. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Transfer Torque MRAM (STT-MRAM) is considered the most promising NVM to address this issue thanks to its high speed, low power, and infinite endurance. However, one of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). In this paper, we propose a power-efficient MFF design architecture to address this challenge based on the combination of checkpointing operation, power gating and self-enable mechanisms. Multi non-volatile storages can be integrated locally in a conventional FF without significant area overhead benefiting from the 3-D implementation of STT-MRAM. We performed electrical simulations (i.e. transient and statistical) to validate its functional behaviors and evaluate its performance by using an accurate spice model of STT-MRAM and an industrial 40 nm CMOS design kit. The simulation results confirm its lower power consumption compared to conventional CMOS FF and the other structures. [ABSTRACT FROM AUTHOR]

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., >10^12) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability. [ABSTRACT FROM AUTHOR]

The miniaturization of integrated circuits based on complementary metal oxide semiconductor (CMOS) technology meets a significant slowdown in this decade due to several technological and scientific difficulties. Spintronic devices such as magnetic tunnel junction (MTJ) nanopillar become one of the most promising candidates for the next generation of memory and logic chips thanks to their non-volatility, infinite endurance, and high density. A magnetic processor based on spintronic devices is then expected to overcome the issue of increasing standby power due to leakage currents and high dynamic power dedicated to data moving. For the purpose of fabricating such a non-volatile magnetic processor, a new design of multi-bit magnetic adder (MA)—the basic element of arithmetic/logic unit for any processor—whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RM)—is presented in this paper. The proposed multi-bit MA circuit promises nearly zero standby power, instant ON/OFF capability, and smaller die area. By using an accurate racetrack memory spice model, we validated this design and simulated its performance such as speed, power and area, etc. [ABSTRACT FROM PUBLISHER]