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Associative processors, while ideal for vector-based applications, have been limited in their use mainly due to area and energy considerations. This reality is changing due to the advent of ultra-dense resistive memories (RRAMs), allowing for area efficient implementations of in-memory associative processors. However, with the high levels of integration, issues related to power density become the major bottleneck. In this paper, we investigate approximate computing in RRAM-based associative processors as a means of enhancing energy efficiency for in-memory associative processors. A case study of a wireless communication system is considered, where fast Fourier transform (FFT) modules are widely used. The proposed manager adjusts the bit width based on the channel SNR, aiming at achieving the desired performance at a reduced energy consumption. An analytical model of system performance under the reduced bit width induced noise is presented. Based on this model, an adaptive bit width adjustment algorithm is presented that utilizes the received SNR estimates to find the optimal bit width that achieves the desired performance goals. Simulation results show that the proposed algorithm can achieve up to 45% energy savings as compared to wireless communication systems using conventional RRAM FFT associative processor. [ABSTRACT FROM AUTHOR]

Emerging technologies have enabled efficient, high-speed realizations of ultra-dense crossbar arrays, driving the need for better insight in the transient operation of such systems. Previous work focused mostly on the effect of line resistance and its impact on steady-state response. In this paper, we develop a compact $RC$ framework that includes the effects of parasitics. We use memristors as an exemplar device where interconnect parasitics (resistance, inductance, capacitance, and conductance) are extracted using ANSYS Q3D extractor for 5- and 50- $nm$ feature sizes. A model for the crossbar is presented, considering the stray and coupling capacitive parasitics of the crossbar. The derived model is based on state-space representation and provides more insight into the behavior of crossbar arrays containing either linear or nonlinear switching devices. The framework provides a closed-form solution to evaluate Elmore delay, as well as the steady-state response of the system. Signal delay is evaluated and compared for both grounded and floating interconnect inputs and verified against HSPICE, showing a perfect match. [ABSTRACT FROM PUBLISHER]

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures. [ABSTRACT FROM AUTHOR]

To guard against process variability in advanced semiconductor nodes, especially for high-density memories, designers resort to overdesigning policies resulting in increased power consumption. A promising approach to save power is to utilize Voltage over-Scaling (VoS). However VoS results into unreliable buffering memories where a predictable statistically amount of errors are introduced to memories. The goal is to trade off channel dependent SNR slack versus hardware induced errors, to achieve predetermined quality metrics, at reduced power consumption. By design, modern communication systems attempt to minimize channel-dependent SNR slack via adaptive modulation and coding (AMC) schemes, thus reducing the gains of on-chip power management. This paper investigates the interaction between on-chip power management via VoS on embedded memories versus network based AMC techniques. A novel mathematical approach that analytically describes the system packet error rate (PER) performance under the VoS induced noise is presented. Based on this model, different AMC and power management algorithms are presented that utilize the received SNR estimates to find the best AMC mode and memory voltage that achieves performance goals at reduced power consumption. Simulation results show that the proposed algorithms can achieve up to 58% energy efficiency for the memory-subsystems compared to conventional AMC algorithm with perfect memories. [ABSTRACT FROM AUTHOR]

In a broadband MIMO-OFDM wireless communication system, embedded buffering memories occupy a large portion of the chip area and a significant amount of power consumption. Due to process variations of advanced CMOS technologies, it becomes both challenging and costly to maintain perfectly functioning memories under all anticipated operating conditions. Thus, Voltage over Scaling (VoS) has emerged as a means to achieve energy efficient systems resulting in a tradeoff between energy efficiency and reliability. In this paper we present the algorithm and VLSI architecture of a novel error-resilient K-Best MIMO detector based on the combined distribution of channel noise and induced errors due to VoS. The simulation results show that, compared with a conventional MIMO detector design, the proposed algorithm provides up-to 4.5 dB gain to achieve the near-optimal Packet Error Rate (PER) performance in the 4 × 4 64-QAM system. Furthermore, based on experimental results, when jointly considering the detector and memory power consumption, the proposed resilient scheme with VoS memory can achieve up to 32.64% savings compared to the conventional K-Best detector with perfect memory. [ABSTRACT FROM AUTHOR]

This paper exploits the predominance of embedded memories in current and emerging wireless transceivers as a means to save power via channel state aware voltage scaling. The paper presents a statistical model that captures errors in embedded memories due to voltage over-scaling and maps the errors to a Gaussian distribution that represents a combination of communication channel noise and hardware noise. Designers can use the proposed model to investigate different power management policies, that capture the performance of the system as a function of both channel and hardware dynamics, thus creating a much richer design space of power, performance and reliability. A case study of a DVB receiver is presented and the validity of the proposed model is confirmed by simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel approach to perform joint detection and decoding for spatial multiplexing multiple-input multiple-output (MIMO) systems which utilize convolutional codes. The bit error rate (BER) performance of the proposed approach is significantly better than that of systems which utilize separate detection and decoding blocks. Formal algorithms with two possible system setups are presented and their performance documented. In particular, for a reference 4 \times 4, 16-QAM system using a rate 1/2 convolutional code with generator polynomial [247, 371] and a constraint length of 8, improvements in signal-to-noise ratio (SNR) of 2.5 dB and 3 dB are achieved over conventional soft decoding at a BER of \ 10^-5. The proof of concept VLSI architecture for one algorithm is provided and a novel way to reduce memory usage is demonstrated. Results indicate that better performance over conventional systems is achievable with comparable hardware complexity. The proposed design was synthesized and layout with 65-nm CMOS technology at 181-MHz clock frequency. An average throughput of 216.9 Mbps at a SNR of 13 dB with area equivalent to 553 Kgates was achieved. [ABSTRACT FROM PUBLISHER]

This paper presents a novel algorithm and architecture for K-Best decoding that combines the benefits of radius shrinking commonly associated with sphere decoding and the architectural benefits associated with K-Best decoding approaches. The proposed algorithm requires much smallerK and possesses the advantages of branch pruning and adaptively updated pruning threshold while still achieving near-optimum performance. The algorithm examines a much smaller subset of points as compared to the K-Best decoder. The VLSI architecture of the decoder is based on a pipelined sorter-free scheme. The proposed K-Best decoder is designed to support a 4\times 4 64-QAM system and is synthesized with 65-nm technology at 158-MHz clock frequency and 1-V supply. The synthesized decoder can support a throughput of 285.8 Mb/s at 25-dB signal-to-noise ratio with an area of 210 kGE at 12.8-mW power consumption. [ABSTRACT FROM PUBLISHER]

The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-mum 1.8-V CMOS technology and requires a total area of 72mm2 consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals [ABSTRACT FROM PUBLISHER]