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This paper reports a $24\times 57$ correlation filter system for object tracking applications. While digital interfacing of the input and output data enabled a standard and flexible way of communication with pre- and post-processing digital blocks, the multiply-accumulate (MAC) operations were performed in the analog domain to save power and area. The proposed system utilizes non-volatile floating-gate memories to store filter coefficients. The chip was fabricated in a 0.13- $\mu \text{m}$ CMOS process and occupies 3.23 mm2 of silicon area. The system dissipates 388.4 $\mu \text{W}$ of power at a throughput of 11.3 kVec/s, achieving an energy efficiency of 25.2 pJ/MAC. Experimental results for a custom filter designed to detect vehicles are presented. [ABSTRACT FROM AUTHOR]

A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-\mum process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 \muV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 \muW of power, or 23 pJ of energy per comparison. [ABSTRACT FROM PUBLISHER]