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This paper presents a 46 nF/10 $\text{M}\Omega $ -range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/ $0.37 \Omega _{\text {rms}}$ resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a $0.18 ~\mu \text{m}$ standard CMOS process, the R2CDC consumes 140 $\mu \text{A}$ from a 1 V supply, occupying an active area of $0.175 ~\mu \text{m} ^{\mathrm{ 2}}$. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new on-silicon-interposer passive equalizer for next generation high bandwidth memory (HBM) with 1024 I/O lines and 8-Gb/s data transmission, which is four times higher than the data rate of HBM generation 2. The proposed equalizer meets the three requirements for the implementation of ultra-high bandwidth interface with wide I/O lines: 1) small area; 2) fine pitch; and 3) low power. The proposed equalizer is embedded in a ground plane on an interposer to reduce additional area consumption. By staggering the equalizers in two rows, 7- $\mu \text{m}$ pitch of the channel can be maintained. The equalizer consumes only 8.24 mW at the data rate of 8 Gb/s since it adopts passive equalization methodology. Robust performance that is independent of insertion location provides design flexibility. The proposed design process for the equalizer helps to reduce manufacturing time and cost. We have verified the performance of the proposed equalizer using simulation and measurement. By applying the proposed equalizer, the eye diagram which was completely closed is successfully open with an eye height of 11.5% $V_{{\mathrm {TX,output}}}$ and an eye width of 57.8% unit interval at a bit-error rate of 10−12. [ABSTRACT FROM AUTHOR]

An energy autonomous active wireless surface acoustic wave (SAW) temperature sensor system is presented in this paper. The proposed system adopts direct temperature to frequency conversion using a lithium niobate SAW resonator for both temperature sensing and high-Q resonator core in a cross-coupled RF oscillator. This arrangement simplifies the temperature sensor readout circuit design and reduces the overall system power consumption. A power conditioning circuit based on buck-boost converter is utilized to provide high efficiency power extraction from piezoelectric energy harvester (PEH) and dynamic system power control. The SAW resonator is fabricated in-house using a two-step lithography procedure while the RF oscillator as well as the PEH power conditioning circuit are implemented in standard 65-nm and 0.18-\mum CMOS processes respectively. The measured RF transmitter output power is -15 dBm with a phase noise of -99.4 dBc/Hz at 1 kHz offset, achieving a figure of merit (FOM) of -217.6 dB. The measured temperature sensing accuracy is \pm \0.6~^\circC in -\40~^\circC to 120 ^\circC range. Fully powered by a vibration PEH, the proposed energy autonomous system has a self-startup voltage of 0.7 V and consumes an average power of 61.5 \muW. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 \mum show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3\times, 19\times, 29\times respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations. [ABSTRACT FROM AUTHOR]

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 \mu s. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V\sim0.6 V by the proposed CAM-assisted circuit. [ABSTRACT FROM AUTHOR]

This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits. [ABSTRACT FROM AUTHOR]

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 \muVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-\mu\ m standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. [ABSTRACT FROM PUBLISHER]

Wireless power transfer provides a safe and robust way for powering biomedical implants, where high efficiency is of great importance. A new wireless power transfer technique using optimal resonant load transformation is presented with significantly improved efficiency at the cost of only one additional chip inductor component. The optimal resonant load condition for the maximized power transfer efficiency is explained. The proposed technique is implemented using printed spiral coils with discrete surface mount components at 13.56 MHz power carrier frequency. With an implantable coil having an area of 25 mm \times\,10 mm and a thickness of 0.5 mm, the power transfer efficiency of 58% is achieved in the tissue environment at 10-mm distance from the external coil. Compared to previous works, the power efficiency is much higher and the structure is compact with planar integration, easy to tune, and suitable for batch production, as well as biocompatible owing to no incorporation of ferromagnetic core. [ABSTRACT FROM PUBLISHER]

A low-power variable-gain amplifier (VGA) based on transconductance (gm)-ratioed amplification is analyzed and designed with improved linearity. The VGA has the merits of continuous gain tuning, low power consumption and small chip area. However, the linearity performance of the gm-ratioed amplifier is usually poor. We analyze distortion in gm-ratioed amplifiers and propose to improve the output linearity by applying load degeneration technique. It is found that theoretically the output linearity can be improved by 8.5 dB at the same power consumption. We also analyze gain, bandwidth and noise performance of the gm-ratioed amplifiers. Two VGAs based on gm-ratioed amplification are designed and fabricated in a 0.18-\mu\ m CMOS process—one with load degeneration only and the other with both input and load degeneration. The VGA with load degeneration only achieves gain of -20 to 41 dB, bandwidth of 121 to 211 MHz, and input and output P1dB up to - 17∼\ dBm and 0.65 dBm, respectively. The VGA with both input and load degeneration achieves gain of -37 to 28 dB, bandwidth of 76 to 809 MHz, and input and output P1dB up to - 2.63∼\ dBm and 2.29 dBm, respectively. The two VGAs consume a similar amount of power, which is about 3 to 5 mW from a 1.8-V supply. For the same bias condition, the proposed load degeneration improves the output linearity by more than 15 dB. [ABSTRACT FROM AUTHOR]