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This paper presents a 220-MHz pulse width modulation (PWM) fully integrated KY dc–dc step-up converter utilizing bondwire as power inductor, with discontinuous conduction mode (DCM) calibration control. We develop the first DCM closed-loop PWM controller for the KY converter, including: 1) its parameter design; 2) a DCM closed-loop voltage mode control with Type II compensator; 3) a zero current detection method to activate DCM control; and 4) a DCM calibration loop. Fabricated in 65-nm CMOS, the designed KY converter core occupies 0.93 mm2 and achieves an output conversion range of 1.5–2 V from a 1.2-V input. The measured peak efficiency is 75.2% at 97.5 mW. With a 500-ps rising/falling time of the load current step (56 mA), the undershoot/overshoot is 245/205 mV at 146-/140-ns recovery time, and the dc–dc converter achieves a settling time per load transient step of 2.6 ns/mA, which is competitive with the state-of-the-art boost converters. [ABSTRACT FROM AUTHOR]

This article presents a compact power management solution for a pipeline analog-to-digital converter (ADC), employing only a switching-mode power converter. By directly powering the ADC using a boost DC-DC converter, the power delivery network (PDN) exhibits an overall-high power efficiency. The proposed foreground ADC calibration calibrates the ripple error induced from the power converter, which obviates the need for well-regulated supply and reference voltage offered by low-efficiency linear low-dropout regulators (LDOs). A chip integrates the boost DC-DC converter and the pipelined ADC with an external power inductor. The prototype, implemented in 65-nm CMOS, occupies 2.34-mm2 of total active area (9.4% - ADC, 2.6% - power controller and switches, and 88% - output capacitance). In the measurement, the boost converter, switching at 31.25MHz, converts a 0.5V input to 1.2V and delivers 22.8mW of power to the pipeline ADC. The boost DC-DC converter supplies all voltage domains, including analog/digital power supply and reference. The resulting overall system power efficiency is 78.6%. Sampled at 500MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 34.7/39.9dB without/with the ripple calibration for an input frequency of 177MHz, respectively. [ABSTRACT FROM AUTHOR]

An ultra-low quiescent current dual-mode buck converter system is designed for IoT application, which includes a double clock time (DCT) and a pulse-width-modulation (PWM) control modes. The proposed DCT mode can reduce the conversion loss over a wide loading range from nA-to-mA and achieve seamless mode transition from DCT to PWM control. Implemented in a $0.18\mu \text{m}$ CMOS, this converter achieves a peak efficiency of 92.7%/94.7% in DCT/PWM and >80% efficiency from $10~\mu $ A to 50 mA (5000x), with a wide input voltage from 2 V to 5 V. A quiescent current of 470 nA including bandgap voltage reference and internal oscillator is achieved. The DCT-to-PWM mode selection mechanism achieves an undershoot of 80 mV at $11~\mu \text{s}$ recovery time when load current jumps from $6.67~\mu \text{A}$ to 50 mA. [ABSTRACT FROM AUTHOR]

This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$. Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming. [ABSTRACT FROM AUTHOR]

This paper presents a digital battery management unit (BMU) with built-in resistance (BIR) compensation, modulated frequency detection (MFD), and multi-mode protection (MMP) techniques to realize fast, efficient and safe charging. The charger incorporates the proposed BMU based on the low-dropout (LDO) regulator. With BIR compensation, a large rated current in the proposed pulsed constant current (PCC) mode charges the battery, and reduces the charging time by omitting the constant-voltage (CV) mode. The MFD technique allows continuous monitoring and obtains precise BIR compensation with accelerating sampling speed. The MMP technique can alleviate safety concerns while charging, including over-voltage protection (OVP), over-current protection (OCP), and the proposed accidental fluctuation protection (AFP). The digital BMU, implemented in 28 nm CMOS, occupies 0.014 mm2 of silicon area. Experimental results show that the proposed circuit saves 73.3% of charging time with 1.5A charging current, and 21.5% ADC dynamic power with 1A charging current. For the digital controller IC, the power consumption is $59.1~\mu \text{W}$. [ABSTRACT FROM AUTHOR]