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The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only $4\times $ redundancy. [ABSTRACT FROM AUTHOR]

This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of <2 adding redundancy and providing ability for gain calibration using a per-column digital multiplication operation. The presented digital feedback correction scheme is applied online and in-column after the end of each conversion, occupying less than 5% of the ramp time. The architecture is verified on a $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion. [ABSTRACT FROM AUTHOR]

This paper presents a low power interference-robust radar transceiver architecture for noncontact vital sign detection and mobile healthcare applications. A duty-cycled transceiver design is proposed to significantly reduce power consumption of front-end circuits. Occupying 3-to-5 GHz band with four 500 MHz sub-channels, the radar mitigates the narrowband interference (NBI) problem with the frequency hopping scheme. In the time domain, the $\Delta \Sigma $ TDC is employed to achieve fine ranging resolution with noise shaped oversampling. The transceiver implemented in 65 nm CMOS consumes 17.2 mW from a 1.0-V supply when duty-cycled and achieves an RMS detection accuracy of 5.68 mm. [ABSTRACT FROM AUTHOR]

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $ . The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform. [ABSTRACT FROM PUBLISHER]

State-of-the-art TDCs can have a precision close to one picosecond, for which reason clock instability is starting to be one of the most significant factor limiting the precision. This paper provides methods to estimate clock jitter induced error by phase noise PSD measurements. Due to the different noise processes of the power-law model, convergence problems might restrict the time domain conversion of clock instabilities. Since time interval measurement corresponds to measuring the first difference of phase error, the convergence problems cannot be completely avoided as is usually done when characterizing frequency instabilities in time domain by measuring the 2nd differences of the phase error. This issue is addressed by taking into account the finite observation window of the phase error. Also a simple PSD measurement technique is introduced to provide an estimate of the jitter due to noise floor with an unknown bandwidth. Spurious tones in the phase noise PSD are also shown to have a significant impact on the precision of a TDC. The results are confirmed by several measurements done with a time-to-digital converter having a 1-ps precision. [ABSTRACT FROM PUBLISHER]

This paper presents an asynchronous digital technique for the realization of an integrator that takes as input the time-difference between two rising edges of digital signals and produces a corresponding time-difference output signal. The key element of this circuit is a time-memory cell called TLatch. This circuit has the ability to store the time-difference between two edges and allow its retrieval at a later time. By using two TLatches in parallel, a dual-path high-throughput integrator is proposed. Internal mismatches in delays can be removed using a simple calibration algorithm that aligns the frequency of two internal oscillators, thereby eliminating the need for trimming or any reference element. The proposed architecture is fabricated in 1.2 V 0.13-μm IBM CMOS technology and the experimental results confirm the integration operation. [ABSTRACT FROM PUBLISHER]

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97∼dBc in-band phase noise, - 38∼dBc/Hz integrated noise, and 740 ns settling time. [ABSTRACT FROM AUTHOR]

As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in fractional-N all-digital phase-locked loops (ADPLLs) have proven them to be competitive with analog state of the art for narrowband applications, demonstrating excellent phase noise and achieving even traditionally difficult standards such as GSM. However, to achieve comparable high performance for wideband applications requires a reduction in fractional spurs. This paper provides a brief summary of ADPLL architectures, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique. Along the way, an efficient simulation model to predict fractional spur amplitude and frequency in ADPLLs is presented. The 3 GHz prototype operates from a flexible reference frequency, between 25 MHz–100 MHz, has in-band phase noise of -101 dBc/Hz with a decade of loop bandwidth programmability, and in-band spurs below -45 dBc. The synthesizer occupies 0.4 \mm^2 in 65 nm digital CMOS and consumes less than 10 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]