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In order to gain substantial circuit performance improvement in terms of power, speed and area cost, approximate computing is ideally applied in many error-resilient DSP and multimedia applications by relaxing the requirements of exact computation. Fixed-width multipliers are intensively used in those applications, which makes them a good demonstration for approximation through dynamic range reduction. In this paper, a probabilistic prediction based fixed-width Booth multiplier has been proposed. The error compensation function is derived from the probabilistic analysis on the partial products obtained from Booth encoding. By slightly modifying the partial product array with dedicated partitioning, a simple compensation circuit is thus formulated. Compared with the previous works, the proposed design exhibits the best performance-accuracy tradeoff. It achieves at least 27% reduction on the area-energy-delay-error product compared with the other multipliers among various operand lengths. Additionally, the evaluation on 2-Dimensional discrete cosine transform (DCT) circuits indicates that our proposed fixed-width Booth multiplier is applicable for lossy applications with a considerable reduction on hardware expenses and power dissipation while maintaining decent output quality. [ABSTRACT FROM AUTHOR]

As computing devices continue growing explosively, computational efficiency is increasingly important. To improve the efficiency of computations, approximate computing is widely used in today’s arithmetic circuits. For simple arithmetic units, manual approximation methods achieved high efficiency. However, with the increasing scale and complexity of the calculation circuit, the approximation efficiency of manual approximation method is gradually reduced and the difficulty of judging the approximate part is also increasing. To this end, automatic approximation methods become especially important. For automatic approximation methods, the key challenge is choosing a metric to guide the approximation process which is easy to calculate accurately and minimize the time spent on it. Therefore, modified optimal slope ranking (OSR) method is proposed in this paper for improving the metric precision and greatly reducing the time cost of approximation process. The simulation results show that the proposed method shows advantages in different circuits, including adders, fixed-width multipliers and DCT. Compared with manual approximation methods, modified OSR method achieves 16.8% lower EDP consumption than competitors on fixed-width multipliers. Compared with our previous work, the proposed method achieves an EDP advantage of 9.17% on DCT at highest accuracy mode. At the lowest accuracy, modified OSR method still maintains certain performance advantages and becomes more obvious as the circuit complexity increases for all precision modes. In terms of time consumption, modified OSR method achieves a speed increase of nearly 10% with the highest precision and a speed increase of up to $7.73\times $ for DCT at the lowest accuracy. In addition, modified OSR also provides flexible precision choices for different application scenarios. [ABSTRACT FROM AUTHOR]