1. A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS.
- Author
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Liang, Jinghang, Zhou, Zhiyin, Han, Jie, and Elliott, Duncan G.
- Subjects
- *
VOLTAGE-controlled oscillators , *COMPLEMENTARY metal oxide semiconductors , *SYSTEMS design , *COMPUTER architecture , *ELECTRIC circuits , *POWER resources - Abstract
A 6.0–13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply. [ABSTRACT FROM AUTHOR]
- Published
- 2013
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