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In the design of sigma-delta modulators ($\Sigma \Delta $ Ms), different variables need to be optimized together in order to maximize the performance. This design task has the added difficulty of dealing with the non-linear behavior of the quantizer. Although a linearized model of the quantizer can be used, this may result in significant discrepancies between the predicted and actual behavior of the $\Sigma \Delta \text{M}$. To better predict the behavior of a given design, we propose a design methodology for $\Sigma \Delta $ Ms based on a genetic algorithm (GA) that uses both linear equations and simulations. In order to reduce the computation time, the design solution is initially evaluated using equations and only if the performance is deemed good enough, it is subjected to a more refined simulation. This more precise simulation takes into account thermal noise, finite output swing, and gain (among other non-idealities) of the building blocks of the modulator. Moreover, Monte Carlo (MC) analyses are performed during the optimization in order to assess the sensitivity to component variations of the solutions. In order to demonstrate the validity and robustness of the proposed optimization methodology, several $\Sigma \Delta $ Ms designs are presented, together with the corresponding measured results. [ABSTRACT FROM AUTHOR]

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ($\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB. [ABSTRACT FROM AUTHOR]