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This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3rd order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden’s and Schreier’s figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear digital decoder (reconstruction filter) for incremental delta-sigma modulators. This decoder utilizes both the magnitude and pattern information of the modulator output to achieve accurate input estimation. Compared to the conventional linear filters with the same oversampling ratio (OSR), it can improve the converter’s signal-to-quantization noise ratio by a few dB to a few 10’s of dB with slight thermal noise performance degradation. Using the proposed decoder, the modulator’s OSR can be a few times less while achieving the same resolution and data rate, thus minimizing the modulator as well as its peripheral circuits’ energy consumption. In this paper, the proposed decoder is optimized for digital implementation, with its function being verified using a modulator prototype. This decoder is mainly designed for dc or near-dc signal conversions and it does not provide frequency notches. [ABSTRACT FROM AUTHOR]

In this paper, we design a no-overloading error feedback quantizer based on a \Delta \!\Sigma modulator, composed of an error feedback filter and a static quantizer. To guarantee no-overloading in the quantizer, we impose an l_{\infty } norm constraint on the feedback signal in the quantizer. Then, for a prescribed l_{\infty }$ norm constraint on the error at the system output induced by the quantizer, we design the error feedback filter that requires the minimum number of bits that achieves the constraint. Next, for a fixed number of bits for the quantizer, we investigate the achievable minimum l_{\infty } norm of the error at the system output with the no-overloading quantizer. Numerical examples are provided to validate our analysis and synthesis. [ABSTRACT FROM AUTHOR]

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phase-locked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 $\rm{{ps}_{rms}}$ and 4.18 $\rm{{ps}_{rms}}$ , while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. [ABSTRACT FROM PUBLISHER]

This paper presents a micropower audio delta-sigma (\Delta\Sigma) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both {g}_{m}/{I}_{D} ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order \Delta\Sigma modulator is implemented in a 0.18 \mu\text{m} CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300-\mu\text{W}$ from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures. [ABSTRACT FROM PUBLISHER]

This paper presents several novel low-power low-distortion \Delta\Sigma modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order \Delta\Sigma modulators with and without noise coupling were analyzed and simulated. [ABSTRACT FROM AUTHOR]

A comparative design study of ultra-low-power discrete-time \Delta \Sigma modulators (DT \Delta \SigmaMs) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order \Delta \SigmaMs are analyzed and compared to a power-optimized standard active modulator (\Delta \Sigma MAA). The first variant (\Delta \Sigma MAP) employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less \Delta \Sigma MPP) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the \Delta \Sigma MAA, \Delta \Sigma MAP, and \Delta \Sigma MPP achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 \muW, 1.27 \muW, and 0.92 \muW, respectively, from a 0.9 V supply. Furthermore, the \Delta \Sigma MPP can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step. [ABSTRACT FROM AUTHOR]

A spread-spectrum clock generator (SSCG) is realized by an under-damping all-digital phase-locked loop (PLL). In this SSCG, the spread-spectrum clocking is achieved by switching the divider without a delta-sigma modulator. By using a digital self-calibration technique, the frequency of this SSCG has a triangular modulation profile and relaxes the process variations. This SSCG is fabricated in a 0.18 \mum CMOS process. The measured electro-magnetic interference reduction is 14.37 dB. The measured rms and peak-to-peak jitters are 1.49 ps and 13.33 ps in a PLL mode, respectively. The measured rms and peak-to-peak jitters are 2.67 ps and 19.90 ps in a spread-spectrum modulation, respectively. [ABSTRACT FROM PUBLISHER]

In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a \Delta\Sigma ADC. The 0.13 \mum CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 \muW power consumption. The conventional ADC has similar performance but dissipates 241 \muW. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step). [ABSTRACT FROM PUBLISHER]

In this paper a 1-V supply, 15-bit ΔΣ ADC design for audio applications is presented. The second order CIFB ΔΣ modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 μm CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 μW and the decimator consumes 170 μW. The core area of the ADC is 0.5 mm2. The modulator occupies 0.3 mm2 and the decimator occupies 0.2 mm2. [ABSTRACT FROM PUBLISHER]

Novel implementation techniques, such as the use of direct-charge-transfer stage, noise coupling, and dynamic element matching can improve the performance of wideband \Delta\Sigma ADCs. However, they introduce extra loop delay, which compromises the low-distortion property and even the loop stability. This paper shows how the addition of independent feedback and feed-forward branches to the loop filter can compensate the extra loop delay, and restore the desired signal and noise transfer functions. The design methodology is then generalized for different kinds of \Delta\Sigma ADCs, and the low-distortion property is analyzed. Two wideband delta-sigma ADCs have been designed and simulated to verify the theory. [ABSTRACT FROM PUBLISHER]

In this paper, a low-voltage fourth-order 2-2 cascade delta–sigma (\Delta\Sigma) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the \Delta\Sigma modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order \Delta\Sigma modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented \Delta\Sigma modulator is fabricated in a 0.18-\mu\m 1P6M CMOS technology. The chip core area without PADs is 1.57 \mm^2. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance. [ABSTRACT FROM PUBLISHER]