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This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the $0.18\mathbf {\mathrm {\mu }}\text{m}$ RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/°C over $\mathbf {-} 40\mathbf {\mathrm {\sim }} 125\mathbf {^{\circ} }\text{C}$ at a 1.8-V supply. The corresponding measured coefficient of variation ($\mathbf {\mathrm {\sigma }}/\mathbf {\mathrm {\mu }}$) is around 0.3%, and the load driving capability can be up to $800\mathbf {\mathrm {\mu }}\text{A}$. By reusing the feedback resistors, the chip prototype achieved a low noise density of $1.92~\mathbf {\mathrm {\mu }}\text{V}/\surd $ Hz, 285nV/ $\surd $ Hz and 4nV/ $\surd $ Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is −39dB at 5Hz and −45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified. [ABSTRACT FROM AUTHOR]

This tutorial brief reviews highly-integrated switched-capacitor (SC) DC-DC converter topologies for miniaturized energy harvesting (EH) IoT systems. Aiming to provide a concise overview of SC converter-based EH interfaces, we first discuss the system level design considerations for energy balancing between source, storage, and load under different environmental conditions. The key factors dominating the energy extraction and power conversion efficiencies, including the source adaptation strategies and SC power stage intrinsic losses, are outlined to establish a fundamental understanding on the EH system performance. After studying different state-of-the-art SC topologies in terms of their rational boost voltage conversion ratio (VCR) generation flexibility, loss characteristics, and implementation tradeoffs, we further introduce two advanced SC converter-based EH system examples, highlighting the SC converter operation in enhancing the EH system functionality and performance. The pros and cons of different SC converter topologies for EH systems will also be discussed. [ABSTRACT FROM AUTHOR]

This brief presents the design methodology of an integrated KY dc–dc step-up converter with constant on-time (COT) control under discontinuous conduction mode (DCM) operation. The method improves the efficiency during the deep-light-load situation, and we analyze the design criteria of the flying capacitor as well as the COT controller of the KY converter under DCM. The simulation results verify that the design obtains higher conversion efficiency than the pulse width modulation controlled KY converter. The KY converter with COT control has been fabricated in 65-nm CMOS with a core area of 0.55 $\times $ 0.55 mm2. The circuit uses an off-chip inductor of 12 nH and an output capacitor of 4 nF. The converter operates with a current load ranging from 500 $\mu \text{A}$ to 10 mA with an output voltage ripple lower than 70 mV in the deep-light-load range. [ABSTRACT FROM AUTHOR]

This brief presents a high efficiency fully integrated high-voltage (HV) pulse driver in standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system employs an optimized 4-stage cross-coupled switched-capacitor voltage multiplier (SCVM) together with an on-chip HV output driver to generate HV pulses of >10 V. We propose an area-efficient HV output driver stage to reach up to 12% total active area reduction when compared with the conventional implementation while maintaining the low static power characteristics. We also present a synchronous charge compensation (SQC) technique to alleviate the loading-dependent signal distortion through reducing the HV rail voltage droop and improving the HV pulse settling time during the driver output transitions. Fabricated in 65-nm bulk CMOS, the chip prototype can successfully generate HV pulses from 250 kHz to 1 MHz with a 15 pF load while ensuring no device breakdown. Measurement results demonstrate a peak SCVM power conversion efficiency (PCE) of 50% and an overall driving efficiency of 12.25%. The chip prototype attains a $\sim 2\times $ faster output pulse transition speed compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

This brief presents a low-power compression-based CMOS image sensor for wireless vision applications. The sensor implements low-bit-depth imaging with planned sensor distortion (PSD) to effectively compress both data bandwidth and processing power while maintaining high reconstruction image quality. Accordingly, a column-parallel microshift-guided successive-approximation-register (SAR) ADC is proposed to enable 3-bit PSD imaging based on a ${3\times 3}$ pattern. To support normal imaging with low area overhead, the circuit is reconfigurable as an 8-bit SAR/single-slope ADC. The data bandwidth is further compressed by a customized lossless encoder based on predictive coding and run length coding. A ${256\times 216}$ prototype imaging system composed of the compression-based image sensor and the lossless encoder is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. Measurement results show that the image sensor achieves 3 bit/pixel (bpp) with 34.9-dB reconstruction peak signal-to-noise ratio (PSNR) and 0.91 structural similarity index (SSIM). With 1/4 spatial downsampling and lossless encoding, 0.31 bpp is obtained with 29.2-dB PSNR and 0.83 SSIM. The sensor consumes $14.8~{\mu }\text{W}$ (full resolution) and $4.3~{\mu }\text{W}$ (downsampling) at 15 fps, achieving state-of-the-art FoMs of 17.8 and 5.2 pJ/pixel $\cdot $ frame, respectively. Including the encoder, the overall system dissipates as low as $1.2~{\mu }\text{J}$ /frame, making it an attractive solution for wireless sensor networks. [ABSTRACT FROM AUTHOR]

This brief presents a 0.9- $\mu \text{W}$ duty-cycle-modulated temperature sensor with a sub- $\mu \text{A}$ peak current for energy harvester- or micro-battery-powered systems. A compact sensing frontend is proposed to achieve low power, together with various device-level leakage and nonlinearity compensation techniques adopted to minimize the sensor error. In addition, a current-starved multivibrator which provides inherent clamping voltages is used for duty cycle modulation for overall energy savings. The sensor designed in 0.18- $\mu \text{m}$ CMOS process achieves a resolution figure of merit of 10.6 pJ $\cdot \text{K}^{2}$ , which is among the most energy-efficient designs to date. Trimmed at 30 °C, the sensor achieves ±0.85 °C precision from −30 °C to 120 °C. The maximum supply sensitivity is 0.7 °C/V for a 1.6–2 V supply. [ABSTRACT FROM AUTHOR]

This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. The input power range with high power conversion efficiency (high PCE) of the rectifier is extended by the proposed architecture, which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65-nm CMOS process. Operating at 900 MHz and driving a 147- \textk\Omega load resistor, the measured PCE of this work can be maintained above 20% with an 11-dB input range from −16 to −5 dBm, while only an 8-dB input range can be achieved with traditional single-path rectifiers. A sensitivity of −17.7 dBm is measured with 1-V output voltage across a capacitive load. [ABSTRACT FROM PUBLISHER]

This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18- \mu\textm CMOS process. It occupies an area of 0.23 mm2 (including the DSL) and consumes 1.7 \mu\textA from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art. [ABSTRACT FROM AUTHOR]

This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load ( CL ) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of CL ; 2) no extra bias circuit and power, as the CM is embedded into the first stage of the amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18- \mu\m CMOS, the amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76- \V/\mu\s average slew rate (SR), and 74^\circ phase margin (PM) at 20-pF CL, and 0.22-MHz UGF, 0.049- \V/\mu\s SR, and 59.8^\circ PM at 15-nF CL. The die size is 0.0045 \mm^2, and power is 32.4\ \mu\W at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art. [ABSTRACT FROM PUBLISHER]