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This brief proposes a 3-stage dual-branch charge pump (CP) with an advanced dynamic gate-biasing technique (DGB) enabling ultra-low-voltage (0.1 V) energy harvesting. Specifically, we reduce the forward conduction loss and the reverse current leakage loss with the combination of an advanced DGB and an NMOS-PMOS dual-switch transistor pair. Also, we investigate the relationship between the pumping capacitance and the power conversion efficiency (PCE) of the CP, thus guiding the PCE improvement with minimal capacitance. The prototype fabricated in 65-nm CMOS achieves a 43.4% PCE at a 0.1-V input voltage. [ABSTRACT FROM AUTHOR]

This Brief reports a cross-coupled differential-drive (CCDD) rectifier with a wide dynamic range (DR) in its power conversion efficiency (PCE). Specifically, it features a self-body-biasing technique to reduce the forward Vth, along with the diode-connected MOSFETs to stem the reverse-leakage current while improving the forward current. The merits of our CCDD rectifier are exemplified via two input-capacitor-coupling configurations: shared-capacitor coupling (SCC) and individual-capacitor coupling (ICC). Fabricated in 0.13-μm CMOS, the SCC-CCDD and ICC-CCDD measure a DR of 13 and 14.5 dB, respectively, for a PCE >40%. Alternatively, the SCC-CCDD exhibits a peak PCE of 83.7% with a sensitivity of −19.2 dBm at 1 V, whereas the ICC-CCDD shows a peak PCE of 80.3% with a sensitivity of −18.7 dBm. [ABSTRACT FROM AUTHOR]

This brief describes a novel Wideband Pre-Distortion (WPD) mechanism as a linearization technique for bandwidth-limited CMOS power amplifiers (PAs). The WPD comprises a common-source amplifier and a hybrid feedback mechanism blended with both active and passive networks to secure a flat gain response from 800 MHz till 3.3 GHz, while maintaining >30% power added efficiency (PAE) at a maximum linear output power of 20 dBm throughout the band of operation. The WPD generates unique gain and phase cancellation mechanisms on-chip therefore alleviating the 3rd-order intermodulation product (IMD3) for an operating bandwidth of 2.5 GHz. Measurement results on 180 nm CMOS, with a supply voltage of 3.3 V indicate that the WPD-PA produces a saturated output power of 24 dBm, in addition to a power gain of 15.5 dB and a peak efficiency of 35.5% at 2.45 GHz. The WPD-PA delivers a maximum linear output power of 20-dBm with an adjacent channel leakage ratio (ACLR) of −30 dBc and error vector magnitude (EVM) of 3.42%, 2.34% and 2.76% at 0.8, 2.45 and 3.3 GHz when measured with the 20-MHz LTE signal. The corresponding maximum linear PAE ranged between 31 to 34%. The chip area is 1.28 mm2. [ABSTRACT FROM AUTHOR]

This brief presents a trim-less precision envelope detector for fail-safe circuit in LVDS receiver. A preamp is proposed using gm-constant biasing concept to produce an accurate gain of 9.78 dB across PVT covering the full range of the LVDS input common-mode voltage. The preamp produces a fixed output common-mode voltage of 200 mV across supply voltage variation which reduces its complexity by alleviating the need of a trimming circuit. A unique reference voltage generation of the envelope detector based on level shifted output common-mode voltage accurately compares the output common-mode and negative peak voltages to set the detection threshold. An LVDS receiver adopting the proposed envelope detector was fabricated on a standard 0.13-μm CMOS. With a supply voltage of 3.3 V, the envelope detector achieves a voltage trimming precision of 20 mV while only consuming 162 μW of power. [ABSTRACT FROM AUTHOR]

This brief models and analyzes the CMOS cross-coupled differential-drive (CCDD) rectifier in subthreshold operation for ambient radio frequency (RF) energy harvesting. The developed model can predict accurately the output voltage against the input RF level, number of stages, transistor size, and output load. For validation, three CCDD rectifiers with 3, 4, and 7 stages, and dissimilar transistor sizes, were fabricated in 0.18- $ {\mu }\text{m}$ CMOS. Each rectifier was tested against different load conditions (10/30/100/500 $\text{k} \Omega $ and open circuit), and input RF levels below the threshold level of the transistor. The verified model has an accuracy of >90% up to 0 dBm input power, and 80% up to 3 dBm input power, across all denoted variations. [ABSTRACT FROM AUTHOR]

This brief reports a class-C mode-switching single-ended-complementary (MS-SEC) VCO for wideband operation. Unlike the existing wideband VCOs that utilize nMOS-only $-\text{g}_{\text{m}}$ transistors operating in the class-B mode to maximize the oscillation amplitude, our MS-SEC VCO combines the advantages of class-C mode, which delivers a tall current pulse, together with current-reuse to maximize the current efficiency while lowering the phase noise (PN). The $-{g}_{m}$ transistors are preserved within the saturation region to avoid the inherent trade-off between PN and power consumption for a wideband VCO, as well as the reliability concerns. The VCO prototyped in 130-nm CMOS occupies a die area of 0.33 mm2 and consumes 5.1-to-7.3 mW at 1.2 V, while covering 2.4-to-5 GHz and meeting the stringent PN specification of the GSM standard with no SAW filter. The results correspond to a figure-of-merit of >190 dBc/Hz throughout the tuning range. [ABSTRACT FROM AUTHOR]