13 results on '"Hussam Amrouch"'
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2. Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries
- Author
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Florian Klemme and Hussam Amrouch
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Hardware and Architecture ,Electrical and Electronic Engineering - Published
- 2022
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3. Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations
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Francisco Javier Hernandez Santiago, Honglan Jiang, Hussam Amrouch, Andreas Gerstlauer, Leibo Liu, and Jie Han
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Hardware and Architecture ,Electrical and Electronic Engineering - Published
- 2022
- Full Text
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4. Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture
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Mikail Yayla, Simon Thomann, Sebastian Buschjager, Katharina Morik, Jian-Jia Chen, and Hussam Amrouch
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Hardware and Architecture ,Electrical and Electronic Engineering - Published
- 2022
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5. Scalable Machine Learning to Estimate the Impact of Aging on Circuits Under Workload Dependency
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Florian Klemme and Hussam Amrouch
- Subjects
Electrical and Electronic Engineering - Published
- 2022
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6. PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits
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Sami Salamin, Hussam Amrouch, Georgios Zervakis, Jorg Henkel, and Yogesh Singh Chauhan
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Materials science ,business.industry ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,Capacitance ,law.invention ,Capacitor ,CMOS ,law ,Logic gate ,Hardware_INTEGRATEDCIRCUITS ,Netlist ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Hardware_LOGICDESIGN ,Negative impedance converter ,Electronic circuit - Abstract
For the first time, we demonstrate an optimization technique to synthesize circuits in the Negative Capacitance FET (NCFET) technology. NCFET is a rapidly emerging technology to replace the currently employed CMOS technology due to its profound ability to overcome the fundamental limit in scaling along with its full compatibility with the existing fabrication process. This is achieved by replacing the traditional transistor gate dielectric with a ferroelectric layer that manifests itself as a Negative Capacitance (NC), which magnifies the electric field. As a result, NCFET-based circuits can operate at a higher clock frequency without the need to increase the operating voltage. NC breaks one of the fundamental laws in physics in which the total capacitance of two capacitors connected in series becomes larger–instead of smaller in ordinary capacitors– than each of them. This could lead to sub-optimal netlists, suffering from significant increase in dynamic power and IR-drops. To suppress that, we employ the relation between delay decrease and capacitance increase of gates w.r.t ferroelectric thickness. Our technique takes an optimized netlist, obtained from commercial EDA tools, and then selectively determines the optimal ferroelectric thickness for each gate in the netlist, so that the maximum performance provided by NCFET is still achieved while the dynamic power is considerably decreased (45% on average), i.e., no trade-offs . Particularly, our technique enables the full exploitation of the performance benefits originating by NCFET, at a significantly lower (power) cost. Compared to state of the art, our technique decreases the energy-delay-product of circuits by 25% on average and reduces the deleterious effects of IR-drop by 56%. Hence, efficiency and reliability of circuits are improved without any loss in the obtained performance from NCFET. more...
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- 2021
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7. Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization
- Author
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Hussam Amrouch and Florian Klemme
- Subjects
Standard cell ,Computer science ,business.industry ,Reliability (computer networking) ,Static timing analysis ,Inference ,Machine learning ,computer.software_genre ,Orders of magnitude (bit rate) ,Dynamic demand ,Artificial intelligence ,State (computer science) ,Electrical and Electronic Engineering ,business ,computer ,Degradation (telecommunications) - Abstract
Aging-induced degradation imposes a major challenge to the designer when estimating timing guardbands. This problem increases as traditional worst-case corners bring over-pessimism to designers, exacerbating competitive and close-to-the-edge designs. In this work, we present an accurate machine learning approach for aging-aware cell library characterization, enabling the designer to evaluate their circuit under the impact of precisely selected degradation. Unlike state of the art, we bring cell library characterization to the designer, empowering their capability in exploring the impact of aging while protecting confidential information from the foundry at the same time. Furthermore, the fast inference of cell libraries makes it feasible, for the first time, to examine aging-induced variability analysis in a Monte-Carlo fashion. Finally, we show that the designer is able to select a less pessimistic timing guardband by choosing adequate delta threshold voltage ( $\Delta {V_{th}} $ ) for their design and their needs. Our machine learning approach reaches an $R^{2}$ score of $>99\%$ for almost all data stored in the cell library. Only timing constraints show slightly less accuracy with an $R^{2}$ score around 95%. When using ML-characterized libraries in static timing analysis, we achieve errors smaller than $\pm 0.5\%$ and $\pm 0.1\%$ for path delay and dynamic power, respectively. Errors in leakage power are negligible and even smaller by orders of magnitude. Our machine learning implementation for standard cell library characterization is publicly available. Download: https://opensource.mlcad.org more...
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- 2021
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8. On the Resiliency of NCFET Circuits Against Voltage Over-Scaling
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Eduardo Costa, Hussam Amrouch, Georgios Zervakis, Yogesh Singh Chauhan, Jorg Henkel, Sergio Bampi, Guilherme Paim, and Girish Pahwa
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Computer science ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,Capacitance ,law.invention ,CMOS ,law ,Logic gate ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Field-effect transistor ,Electrical and Electronic Engineering ,Electronic circuit ,Voltage ,Negative impedance converter - Abstract
Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology. Our work reveals that circuits implemented using the NCFET technology exhibit much less timing errors under VOS due to the inherent voltage amplification provided by the ferroelectric layer. NCFET is one of the very promising emerging technologies that is rapidly evolving for low-power circuit as it enables the transistors to switch faster without the need to increase the voltage. We demonstrate how NCFET technology allows circuit designers to effectively employ VOS to boost the efficiency of their approximate circuits, while still keeping the induced errors marginal. Our analysis shows that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease and thus, NCFET based VOS approximate circuits achieve from $1.83\times$ up to $2.78\times$ higher energy reduction compared to the corresponding FinFET circuits for the same error bounds. more...
- Published
- 2021
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9. Weight-Oriented Approximation for Energy-Efficient Neural Network Inference Accelerators
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Jorg Henkel, Iraklis Anagnostopoulos, Hussam Amrouch, Zois-Gerasimos Tasoulas, and Georgios Zervakis
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Artificial neural network ,Computer science ,020208 electrical & electronic engineering ,Inference ,02 engineering and technology ,Energy consumption ,Object detection ,020202 computer hardware & architecture ,Convolution ,Computer engineering ,Feature (computer vision) ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Throughput (business) ,Efficient energy use - Abstract
Current research in the area of Neural Networks (NN) has resulted in performance advancements for a variety of complex problems. Especially, embedded system applications rely more and more on the utilization of convolutional NNs to provide services such as image/audio classification and object detection. The core arithmetic computation performed during NN inference is the multiply-accumulate (MAC) operation. In order to meet tighter and tighter throughput constraints, NN accelerators integrate thousands of MAC units resulting in a significant increase in power consumption. Approximate computing is established as a design alternative to improve the efficiency of computing systems by trading computational accuracy for high energy savings. In this work, we bring approximate computing principles and NN inference together by designing NN specific approximate multipliers that feature multiple accuracy levels at run-time. We propose a time-efficient automated framework for mapping the NN weights to the accuracy levels of the approximate reconfigurable accelerator. The proposed weight-oriented approximation mapping is able to satisfy tight accuracy loss thresholds, while significantly reducing energy consumption without any need for intensive NN retraining. Our approach is evaluated against several NNs demonstrating that it delivers high energy savings (17.8% on average) with a minimal loss in inference accuracy (0.5%). more...
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- 2020
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10. Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level
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Victor M. van Santen, Hussam Amrouch, and Jorg Henkel
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Computer science ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,Upper and lower bounds ,Noise (electronics) ,law.invention ,Reduction (complexity) ,Reliability (semiconductor) ,CMOS ,Hardware and Architecture ,law ,Electronic engineering ,Electrical and Electronic Engineering ,Electronic circuit ,Random dopant fluctuation - Abstract
Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is observable right after manufacturing, such as geometric variations, work function, and random dopant fluctuation. This is in contrast to time-dependent variability (TDV), i.e., differences in the defects of transistors, which is not macroscopically observable immediately after manufacturing. In fact, defects are electrically neutral until they capture a carrier [with mechanisms called bias temperature instability (BTI) and random telegraph noise (RTN)] and thus become observable through their induced degradation. Therefore, transistors which are characterized identically after manufacturing will drift apart during their lifetime, as their susceptibility to effects such as BTI and RTN is different. In this paper, we model for the first time TDV from a defect-centric physical perspective all the way to the circuit level. Our novel defect-centric transistor reliability specification provides a fast, yet accurate method to estimate an upper bound for TDV on the transistor level, while our novel worst cell (WCL) and worst value (WVL) libraries allow for fast evaluation of the impact of TDV on the timing of circuits. Our approach is fully compatible with existing EDA tool flows, allowing us to model and optimize complex circuits like full microprocessors. By evaluating the impact of TDV with our reliability specification and variability-aware cell libraries, we are able to model TDV, which allowed us to reduce the required defect variability guardband by 46%. In addition, we provide design optimization strategies on each abstraction level such as limiting continuous stress, transistor hardening, and implement a novel variability-aware synthesis to achieve up to 57% additional guardband reduction. more...
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- 2019
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11. Automated Design Approximation to Overcome Circuit Aging
- Author
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Georgios Zervakis, Kostas Siozios, Hussam Amrouch, Jorg Henkel, and Konstantinos Balaskas
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FOS: Computer and information sciences ,Computer science ,Transistor ,Image processing ,Hardware_PERFORMANCEANDRELIABILITY ,Propagation delay ,law.invention ,law ,Logic gate ,Hardware Architecture (cs.AR) ,Netlist ,Electronic engineering ,Electrical and Electronic Engineering ,Computer Science - Hardware Architecture ,Resilience (network) ,Degradation (telecommunications) ,Electronic circuit - Abstract
Transistor aging phenomena manifest themselves as degradations in the main electrical characteristics of transistors. Over time, they result in a significant increase of cell propagation delay, leading to errors due to timing violations, since the operating frequency becomes unsustainable as the circuit ages. Conventional techniques employ timing guardbands to mitigate aging-induced delay increase, which leads to considerable performance losses from the beginning of the circuit’s lifetime. Leveraging the inherent error resilience of a vast number of application domains, approximate computing was recently introduced as an aging mitigation mechanism. In this work, we present the first automated framework for generating aging-aware approximate circuits . Our framework, by applying directed gate-level netlist approximation, induces a small functional error and recovers the delay degradation due to aging. As a result, our optimized circuits eliminate aging-induced timing errors. Experimental evaluation over a variety of arithmetic circuits and image processing benchmarks demonstrates that for an average error of merely $5\times 10^{-3}$ , our framework completely eliminates aging-induced timing guardbands. Compared to the respective baseline circuits without timing guardbands (i.e., iso-performance evaluation), the error of the circuits generated by our framework is $1208\times $ smaller. more...
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- 2021
- Full Text
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12. Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV
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Victor M. van Santen, Jorg Henkel, Hussam Amrouch, Montserrat Nafria, and Javier Martin-Martinez
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010302 applied physics ,Engineering ,business.industry ,Transistor ,Electrical engineering ,02 engineering and technology ,Unified Model ,01 natural sciences ,Noise (electronics) ,020202 computer hardware & architecture ,law.invention ,Process variation ,Reliability (semiconductor) ,law ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Static random-access memory ,Electrical and Electronic Engineering ,business ,Scaling ,Voltage - Abstract
Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages ( $V_{\text {dd}}$ ) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with $V_{\text {dd}}$ , mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with $V_{\text {dd}}$ and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal $V_{\text {dd}}$ and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow $V_{\text {dd}}$ -scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits. more...
- Published
- 2018
- Full Text
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13. Variability-Aware Approximate Circuit Synthesis via Genetic Optimization
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Konstantinos Balaskas, Florian Klemme, Georgios Zervakis, Kostas Siozios, Hussam Amrouch, and Jorg Henkel
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Hardware and Architecture ,Electrical and Electronic Engineering - Full Text
- View/download PDF
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