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This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

An important issue in wireline receivers (RX) is minimizing the area and power consumption while overcoming the channel attenuation with an equalizer. The greater the compensation for channel loss at the analog front end (AFE) of the RX, the lower the number of decision feedback equalizer (DFE) taps. Power dissipation and area can be reduced by reducing the number of DFE taps. This paper presents a technology that compensates for the channel loss with the proposed AFE based on a two-stage continuous-time linear equalizer (CTLE), low and high bandwidth amplifiers, and a gain controller. It sufficiently reduces the DC gain and increases the peak gain of the AFE by using a feedforward equalizer (FFEQ) and feedback equalizer (FBEQ). These equalizers result in an increase in the difference between the peak and DC gains and the gain difference at the fundamental frequency (f0) and 2nd subharmonic frequency (f1/2). The IC is fabricated in a 28 nm CMOS process, and the proposed architecture yields a BER less than 10-12 at 25.8 dB channel attenuation. At 25 Gb/s, the area and power efficiency of the proposed AFE are 1.19 pJ/bit and 0.01 mm2, respectively.

This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an equalizer adaptation loop. A pulse generator in the proposed equalizer obviates the need for additional error sampling comparators. Instead, it allows the receiver to utilize an output of a data decision comparator for the equalizer adaptation by generating a pulse that indicates whether the comparator makes a firm decision for the incoming data. A single comparator is shared by the data recovery path and equalizer adaptation loop. Consequently, the proposed counter-based equalizer achieves a low power dissipation owing to the reduced number of comparators. Fabricated in a 28-nm CMOS technology, the prototype receiver occupies an active area of 0.004 mm2 and consumes only 0.99-pJ/b at 15-Gb/s.

In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.

The timing skew between signals reduces the timing margin of the receiver and limits the data rate of the parallel link. This issue becomes more critical for applications with many IO pins, such as a high bandwidth memory (HBM). The inter-signal skew compensation scheme for many IO pins requires not only de-skew performance but also the minimization of area and power overheads. In this brief, we propose an inter-pin skew compensation scheme using bypass-controlled all digital delay locked loops (ADDLL). The adoption of the proposed bypass control register that operates with a binary search algorithm, such as the successive approximation register (SAR), allows the digital control delay line (DCDL) controller to be embedded in the delay line. This can alleviate the limitation of bandwidth, which is a disadvantage of SAR and occupies smaller area than SAR whereas maintaining the fast lock time. The circuit is fabricated using a 28 nm CMOS technology with a 1 V supply voltage and an area of 0.0009 mm2 for one de-skew module. The measured result shows that inter-signal skew is reduced to less than 3 ps for 2 Gb/s/pin $\times8$ parallel signals.

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes $3.09~{\boldsymbol{\mu }}\text{W}$ . The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10−12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( $ {f}_{{\text {LBW}}}$ ). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$ . A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

A spread-spectrum clock generator is implemented using a nested modulation profile to reduce the peak power levels of radiated electro-magnetic emissions in display products. The display data interface is a potential source of interference, and the spread spectrum technique has been extensively used for display interfaces. The proposed nested profile can further reduce electro-magnetic interference without any degradation in the other characteristics. A test chip was fabricated using a 55-nm CMOS process, and the test results indicate a 41-dB reduction. The sensitivity of a wireless receiver to interference is tested, and the EVM results for the proposed nested profile exhibits an improvement of 1.4 dB compared to those of the triangular profile.

A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for a point-to-point post-low-power mobile DRAM4 interface at 8 Gb/s. AC termination at the RX I/O can reduce the power consumption by preventing dc power loss. However, this causes inter symbol interference (ISI), owing to the difference in gain depending on the frequency. Thus, ac termination generates more jitter, which results in a smaller eye-opening than the conventional on-die termination. The AIP in the TX output driver reduces the low-frequency gain and the ISI caused by the ac termination. This reduces the jitter and improves the eye-opening. The proposed AIP allows changing the frequency range by adjusting the resistance ( ${R}_{\mathrm{AI}}$ ), capacitance ( ${C} _{\mathrm{AI}}$ ), and the size of the MOSFET according to the resistance ( ${R} _{\mathrm{ac}}$ ) and capacitance ( ${C} _{\mathrm{ac}}$ ) used in the ac termination at the RX. In this brief, the ac termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3-inch FR4 microstrip line including a board and a socket model. The proposed transceiver chip achieves a peak-to-peak jitterof 43.6 ps and power reduction of 31% compared with chips without ac termination and AIP.

This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio ( ${\delta }$ ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a −104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13- $\mu\mbox{m}$ CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11- $\mu\mbox{m}$ CMOS process, occupies 0.033 mm2.

This brief presents an energy-harvesting system that uses an adaptive maximum power point tracking (MPPT) circuit for 1-mW solar-powered wireless sensor networks. The proposed MPPT circuit exploits a successive approximation register and a counter to solve the tradeoff problem between a fast transient response and a small steady-state oscillation with low-power consumption. The proposed energy-harvesting circuit is fabricated using a 0.35-μm CMOS process. The MPPT circuit reduces the transient response time by 76.6%, dissipates only 110 μW , and shows MPPT efficiency of 99.6%.

This brief presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450 nW; thus, the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-?m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-mum CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.