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This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs. Index Terms--Barrel shifter, coordinate rotation digital computer (CORDIC), extended range, low area and high throughput implementation.

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex. Index Terms--Field-programmable gate array (FPGA), low-pass (LP) delta-sigma (DS), RF transmitter.

Although the maximum-likelihood decision-feedback equalization (ML-DFE) detection method for multi-input multioutput (MIMO) system leads to a good compromise between the performance and the complexity, the computational complexity of the ML part in the ML-DFE is still large. This paper describes a modified maximum-likelihood (MML) algorithm, which reduces the computational complexity of the original ML algorithm significantly without degrading the performance. Then, based on the MML algorithm, we propose the MML-DFE, which has the same performance as the ML-DFE but has much lower complexity. Both the ML-DFE block and MML-DFE block for 4 x 4 MIMO system have been implemented in field-programmable gate array to verify the functional correctness and the complexity advantage. Index Terms--Decision-feedback equalization (DFE), maximum-likelihood (ML) detection, muiti-input multi-output (MIMO).

Low complexity and reconfigurability are two key requirements of channel filters in a software defined radio receiver. A new reconfigurable architecture based on frequency response masking (FRM) technique for the implementation of channel filters is proposed in this paper. Our architecture offers reconfigurability at filter and architecture levels, in addition to the inherent low complexity offered by the FRM technique. The proposed reconfigurable filter has been synthesized on 0.18-[micro]m CMOS technology and implemented and tested on Virtex-II 2v3000ff1152-4 field-programmable gate array. Synthesis results show that the proposed channel filter offers average area and power reductions of 53.6% and 57.6%, respectively ,with average improvement in speed of 47.6% compared to other reconfigurable filters in literature. Index Terms--Channel filters, frequency response masking (FRM), low complexity, reconfigurability, software defined radio (SDR).