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The electrical endurance of an electromagnetic alternating current (ac) contactor can be reflected by the mass loss of its contacts during operations. This paper carries out ac contactor endurance tests in which arcing phase angles (APAs) are fixed. Contact mass losses are measured, and the electrical signals of the contactor circuit are acquired. Thus, the corresponding energies of each break process are computed. This paper investigates the relation of arcing phases, arcing energies, and mass losses of break processes, and concludes that the higher arcing energies cause greater contact mass losses. Then, this paper proposes a breaking strategy that controls the APAs to minimize and balance the contact mass losses of the three phases of an ac contactor. Therefore, the erosion on each contact is reduced and the total operation number can be increased. Compared with random breaking, the novel strategy significantly improves the electrical lifetime of the ac contactors. [ABSTRACT FROM AUTHOR]

As more circuit functions are integrated within a single die or small integrated package, the number of electromagnetic interference (EMI) problems caused by dc–dc converters is growing. In this paper, the dominant electromagnetic emission source on the dc–dc converter is identified by analyzing the power spectrum of the nodes. The noise scanner method is applied to a packaged single-chip prototype dc–dc converter. The results show that the dominant source of electromagnetic emission is the switching node of the converter, not the output node. The frequency hopping technique (FHT) is applied to the dc–dc converter to reduce the emission at the switching node, and its effectiveness is analyzed mathematically and experimentally. The mathematical model of FHTs is proposed to analyze its effectiveness in reducing EMI, and the optimal design using the FHT and dead-time control is fabricated with 0.18- \mu \textm CMOS technology. The measured power spectrum reduction by using the optimal FHT design and dead-time control at the switching node is 16 dB. The EMI reduction amount of the proposed design measured by the IC-stripline method is 12.6 dB at the fundamental switching frequency. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a switched-beam four-element antenna array operating at 60 GHz for wireless data transfers between chips in a multichip computing system. The antenna-in-package uses a patterned artificial magnetic conductor to enhance antenna performance. The four-element array has a switchable pattern and shows improved transmission gain compared to previous designs used for data communication between chips. The impact of the array configuration on the switching of the antenna pattern is presented. The wireless link power received between TX and RX nodes is used to evaluate the four-element array antenna design. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

A simultaneous switching current (SSC) drawn by an integrated circuit (IC) creates simultaneous switching noise on power nets, which in turn causes jitters in the I/O signals and reduces the maximum clock frequency. For a thorough analysis of high-speed ICs, there is a dire need to measure currents at specific power pins of the ICs. In this paper, a novel magnetically coupled embedded current probing structure is proposed for measuring the SSC on the chip level resulting from the logical activity of the I/O buffers. SSCs are found by capturing the magnetic flux induced by the SSC of interest, with the proposed embedded current probing structure using magnetic coupling, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of measurements with test vehicles fabricated on the chip level, we experimentally verified the proposed probing structures in the time and frequency domains and proved that they can effectively measure the SSC. Finally, future directions for improvements are discussed at the end of this paper. [ABSTRACT FROM PUBLISHER]

The reignition of the arc during the interruption process deteriorates the switching performance of low-voltage switching devices (LVSDs). Avoiding reignition is thus a key goal in the effective design of the quenching chamber. A reliable evaluator of reignition provides the opportunity to predict the switching performance of an LVSD during the design process and to refine the product prior to manufacture and empirical device testing. In this paper, reignition evaluators are investigated through the analysis of interruption test data for several types of LVSDs under the single-phase and three-phase circuit conditions. It is observed that the ratio of the recovery voltage to exit arc voltage, where exit arc voltage is defined as the value of the arc voltage immediately prior to the current zero point, is a reliable evaluator for the prediction of reignition in the switching tests of LVSDs. It is also noted that there are no occurrences of instantaneous reignition where this voltage ratio lies in the range from 1 to −1, and there is a threshold of the voltage ratio at approximately −2, which can distinguish the successful interruption and instantaneous reignition. [ABSTRACT FROM AUTHOR]

This paper presents and discusses results of analysis from investigations of arc-to-glow transformation phenomenon at contact opening, under dc low-energy ( $\leq 10$ J) and low-voltage ( $\leq 250$ V) inductive loads. Dependence of the duration of arcing and glowing on current magnitude, voltage magnitude, properties of the contact material, gas quenching medium velocity and its pressure, as well as contact opening velocity and contact gap are investigated. The transition phenomenon of arc-to-glow is analyzed by means of fast photography and emission spectroscopy. Also discussed is the theoretical evaluation of conditions of arc instability. From the results, possible procedures are formulated to control the arc-to-glow transformation for practical use in dc low-voltage and low-power electrical grids. [ABSTRACT FROM AUTHOR]

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology. [ABSTRACT FROM AUTHOR]

In this paper, the design of RF transceiver front-end using a novel multifunction microwave circuit is proposed. By designing one arm of the proposed active bandpass switchplexer as a bandpass power amplifier (PA) and the other arm as a single-to-balanced bandpass low-noise amplifier (LNA), the resulted multifunctional microwave filtering device thus effectively integrates the functions of single-pole-double-throw RF switch, bandpass filter, balun, PA, and LNA. In this way, all the function blocks between the antenna and up/down converters of a single-band time-division duplex transceiver front-end can be integrated into a single circuit. Compared to the previous works on multifunction microwave circuit designs, the proposed active bandpass switchplexer features the highest number of integrated functions. A printed circuit board-based design example of the proposed active bandpass switchplexer is presented to validate the proposed design concept and to demonstrate the performance achieved. [ABSTRACT FROM PUBLISHER]

Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper. [ABSTRACT FROM PUBLISHER]

Recently, a growing number of dc systems exist based on the development of electrical energy consumption. For low-voltage dc grids, switching devices are needed that have to meet technically sophisticated requirements. These devices have to handle fault currents of several hundred amperes and system voltages up to 1000 V. A typical dc circuit breaker has to provide low on-state losses, light weight, and small volume. On the way toward fulfilling these requirements, hybrid circuit breakers can represent the optimal solution. A hybrid dc circuit breaker combines the advantages of mechanical contacts and semiconductors. In this paper, such a device has been designed and constructed using a commercial switch and electronic components in the laboratory. The breaking performance of this experimental prototype has been investigated, and thus the interruption of the nominal and failure currents in the case of different time constants can be identified. The investigated hybrid switching device has been optimized in order to maximize the switching capacity and the protection of the semiconductors. [ABSTRACT FROM PUBLISHER]

This paper presents an approach for the transient simulation of I/O buffers described by IBIS models. Using the latency insertion method, a formulation can be obtained for the transient behavior of IBIS models combined with external circuitry. The formulation offers better convergence than traditional Newton–Raphson methods and is therefore more robust. The method also implements the BIRD95 and BIRD98 updates that account for predriver current, simultaneous switching noise, and gate modulation effects. Several computer simulations are performed to validate the method. [ABSTRACT FROM AUTHOR]

In this paper, a new method is proposed to model the simultaneous switching noise (SSN) using time-domain impedance function, which is based on the rational function in time domain. The time-domain impedance function of a power delivery network (PDN) is calculated by approximating the impedance frequency response of a PDN with a rational function, and the SSN is calculated based on switching current characteristics, which is verified by advanced design system, Hspice and measurements. Based on time-domain impedance function, the SSN suppression is also investigated, and it is found that the SSN produced by periodic switching current can be suppressed through adjusting the periods of time-domain impedance function and switching current, and a principle for random switching current is also given to prevent the occurrence of the worst case of SSN in circuit design. [ABSTRACT FROM AUTHOR]

High voltage switches capable of operating at high speeds with high current levels are used in a variety of applications in commercial and government systems. This paper discusses the fabrication and characterization of a novel micromachined planar triggered spark gap switch. The switch provides a low cost alternative to conventional triggered spark gap switches. The structure is designed for direct integration into the strip-line geometries used in a conventional capacitive discharge unit. The geometry of the device was selected to minimize parasitic impedances associated with conventional firing circuits. [ABSTRACT FROM PUBLISHER]

Simultaneous switching noise (SSN) is verified as a serious impact on the quality of power distribution and accuracy of the data acquisition system in the mixed signal circuits by modeling and simulating the single-stage output buffer at the driver side. To reduce SSN, a board-level slit-surface disturbance lattice electromagnetic bandgap structure is proposed. The corresponding 1-D equivalent transmission line model is established and lower and upper bound cutoff frequencies of the bandgap are derived. Suitable test boards are fabricated and measured to demonstrate the accuracy of the design concept. The measured SSN reduced to 65% and the signal jitter is decreased by 75% comparing with the solid power/ground plane, which proves that the isolation between the analog and the digital signals can be enhanced to improve the quality of power distribution, and provides a new method to improve precision for data acquisition and transmission in power monitoring system. The results show that the simulated, modeled, and measured results are consistent. [ABSTRACT FROM AUTHOR]

Gold is commonly used for microelectromechanical electrical contacts due to its desirable electrical and mechanical properties; however, the lifetime of gold contacts is limited, particularly in the case of hot switching. To improve the lifetime of electrical contacts, we have developed a gold-coated multiwalled carbon nanotube bilayer composite. Experiments with these composites have shown that the switching dynamics vary over the lifetime of the switch. The change in potential across the switch contacts during the contact-break process, referred to as the transient opening voltage, has been monitored at a number of intervals throughout the switch life. The transient opening voltage shows behavior indicative of the molten metal bridge (MMB) phenomenon. While stable for most of the contact lifetime, the duration of this behavior increases sharply as the contacts approach failure. Throughout the switch lifetime, the contacts are required to survive a large number of opening and closing cycles and, therefore, it is important to understand the switching dynamics. A contact pair was investigated to failure where the experimental conditions were: load current and voltage of 50 mA and 4 V, respectively. Failure occurred after 28 million hot-switched cycles. The average energy of the MMB process was evaluated as 1.54 \mu \textJ per opening event during the stable region, this rose to 13.2 \mu \textJ shortly before failure. An experiment run under similar conditions but with a lower load current of 10 mA, which was switched for over 500 million cycles, showed a stable contact resistance and an average MMB energy of $5~\Omega $ and 57 nJ, respectively. [ABSTRACT FROM AUTHOR]

A hermetic multichip power package for silicon carbide devices that will operate at 200^\circC ambient and switch 50–100 A has been developed. The Al2O3/MoCu structure, in which the SiC junction field-effect transistors and diodes are attached, was designed to hermetically seal the device areas. Details of the materials and processes used to fabricate the package are discussed. Die attach, ribbon bonding, and lid attach, as well as thermal modeling, electrical testing, and thermal cycling results are also described. [ABSTRACT FROM PUBLISHER]

Raised strips were introduced into the micromachined acceleration switch to avoid the stiction between the mass and the substrate. The system spring constant of the switch with serpentine springs was calculated. The influence of the introduced anti-stiction raised strips on squeeze-film damping of the switch was analyzed closed-form using reasonable boundary conditions. Based on the calculated systems parameters, a Simulink model was constructed to simulate the dynamic properties of the switch under different types of shock acceleration. It is indicated that the dynamic responses (threshold acceleration and response time) were almost not affected by those raised strips which are instead beneficial to reduce the oscillation of the moving mass and improve the yield of the switch. Dependence of dynamic properties on the distance between two electrodes, thickness of the mass and spring constant has also been simulated. The drop hammer experiment was conducted to characterize dynamic properties of the fabricated and packaged acceleration switch. Test threshold acceleration and response time are, respectively, about 41 g and 0.7 ms when the half-sine wave shock was applied, which are in accordance with simulated ones. The package strength of the switch was also evaluated and corresponding critical shear stress for failure is about 22 MPa. [ABSTRACT FROM PUBLISHER]