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In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented. The methodology is proven to be applicable to analyze the temperature evolution of real devices. A low-power package configuration with two different power dissipation scenarios, hotspot (HS) in the corner and HS in the center of the active region, has been considered for the validation. In this way, the importance of the package thermal impact on the definition of the final temperature profiles is highlighted. The error between the measurement and the FTM results remains always below 2.3 °C/W. Moreover, the model has been validated with respect to case studies concerning duty cycles of different durations. This proves the applicability of the model in defining the allowed duration of the chip activity before a maximum threshold temperature is reached. Finally, in this paper, the possibility to use a variable time-step approach in the transient FTM is presented together with the option of computing the temperature in individual points only. This is possible maintaining the same accuracy as if the fully resolved temperature maps would be calculated. [ABSTRACT FROM AUTHOR]

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips. [ABSTRACT FROM PUBLISHER]

Accurate peeling off and transferring of microchips play a critical role in LED die sorting technology. Generally, sorting efficiency of more than 36 KUPH, and an alignment deviation less than 1 mil ($25.4~\mu \text{m}$) is required. High precision position control and cooperation of multifactors should be implemented precisely. Among all the factors, the film deformation is an important one. As the sorting proceeds, dies are peeled off from substrates one by one, and the adhesive substrate is penetrated through a hole each time. As the number of stripped chips increases, viscoelastic deformation of tape surface takes place and tiny position shift of die adhered on tape arises. This shift may cause a negative impact on the peeling process. In this paper, linear viscoelastic deformation impact is tested with well-designed experiments. To evaluate the effect of tape deformation accurately for sorting the performance, stochastic Petri net model of the transferring system with dual-independent arms is formulated to analyze the influence of factors. On this basis, strategy on coordinating motion control and scheduling is proposed, rational velocity section is planned, and the active position compensation of supply platform is set, so that the die can be peeled off correctly and efficiently. Finally, to improve sorting performance, methods on active compensation of aligning platform are proposed and proven effective by an experimental validation. [ABSTRACT FROM AUTHOR]

The dependence of self-inductance and mutual inductance on bonding wire (BW) geometric profile has been studied in several papers. This paper will present a method using a BW-geometric-profile-dependent term to include this dependence in a simple model of BWs. The model element values will be calculated only from geometric dimensions. An experimental structure of two BWs in parallel planes has been fabricated based upon glass substrate technique for verification. A good agreement was obtained up to 8 GHz in comparison to electromagnetic simulation and measurement. [ABSTRACT FROM AUTHOR]

In this paper, 2.5-D integrated circuits (ICs) using bridge-chip technology are thermally evaluated to investigate thermal challenges and opportunities for such multi-die packages. To this end, the objectives of this paper are twofold. First, thermal benchmarking of a number of 2.5-D integration approaches is performed and compared to 3-D ICs for completeness. Thermal modeling shows that the evaluated 2.5-D integration approaches exhibit similar thermal characteristics, but show significant improvements compared to 3-D IC solutions with the same power consumption. Second, this paper explores bridge-chip-based 2.5-D integrated systems as a function of bridge-chip thickness, thermal interface material properties, microbump properties, die thickness, die thickness mismatch, and die-to-die spacing along with transient analysis to investigate time-domain thermal coupling. Results suggest that a die thickness mismatch of 100 \mu \textm can increase the maximum temperature by 25.8% Therefore, the die thickness mismatch should be kept as small as possible, and the hottest die should be the thickest. Moreover, reducing die-to-die space from 1 to 0 mm increases thermal coupling, and the low-power dice, such as DRAM, can have a temperature increase of 6.1%. [ABSTRACT FROM PUBLISHER]

In this paper, we have shown an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail. This scaling method will also provide the optimum package solutions to minimize the cost of IC products. This method can be very useful to determine the package and die design methodology at the initial phase of the design cycle of the chip. [ABSTRACT FROM AUTHOR]

The 3-D integrated circuits (3-D ICs) are emerging as a viable solution to enhance the performance of many-core platforms. These architectures generate a high and rapidly changing thermal flux that makes conventional air-cooled devices more susceptible to overheating. Liquid cooling is an alternative that can improve dissipation and reduce thermal issues. Fast and accurate thermal models are needed to appropriately dimension the cooling system at design time. Several models have been proposed to study different designs, but generally with low simulation performance. In this paper, we present an efficient model of the transient thermal behavior of liquid-cooled 3-D ICs. This paper presents an approach with extremely low memory usage and advanced numerical methods to efficiently compute the transient temperature of 3-D ICs. Our experiments show the $100\times $ speedup versus the state-of-the-art models, while maintaining the same level of accuracy, and demonstrate the efficiency of liquid cooling to remove the heat from 3-D many-core platforms. [ABSTRACT FROM PUBLISHER]

Based on the extracted resistance, inductance, capacitance, and conductance parameters, this paper introduces the distributed transmission line model of silicon-core coaxial through-silicon vias (CTSVs), in which the vertical interconnect is made of a Cu-coated silicon pole. The proposed model is validated against a commercial electromagnetic simulation tool, showing it is highly accurate up to 100 GHz. Using the proposed model, the impact of various material properties and physical parameters on the electrical performance of the silicon-core CTSVs is investigated. It is observed that the thickness of the plated Cu and isolation dielectric are two important parameters that determine the electrical performance of silicon-core CTSVs. Performance comparison shows that the proposed silicon-core CTSVs provide a comparable performance to standard Cu-based CTSVs and better performance to the conventional signal-ground TSV pairs. The results in this paper would provide some design guides for silicon-core CTSVs in 3-D integration. [ABSTRACT FROM AUTHOR]

In this paper, a novel input/output (I/O) coupling multiplier circuit for conveniently increasing I/O coupling of a wideband coupled-resonator filter/diplexer is proposed. The multiplier circuit consists of a shunt capacitor and a negative phase shift. By appropriately shunt connecting a capacitor in the vicinity of an I/O port, the I/O coupling can be effectively increased. Compared to conventional approaches of increasing I/O coupling for a wideband application, using the multiplier circuit allows much less perturbing the resonant frequency of the first resonator. For many resonator configurations such as helical resonator, to which the tapping probe could not be adjusted continuously, the multiplier circuit provides a convenient way to control I/O coupling. In this paper, the working mechanism of the proposed circuit is well proved theoretically. The usefulness of the multiplier circuit has been demonstrated for coaxial combline cavity resonators and helical resonators, both for filter and diplexer applications. As a practical example, the multiplier circuit is applied to a wideband UHF helical resonator diplexer. [ABSTRACT FROM PUBLISHER]

A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 \,\,\text mm \times 8 \,\,\text mm \times 0.53\,\, \text mm and 2 \,\,\text mm \times 2\,\,\text mm \times 0.1 \,\,\text mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton, Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm. [ABSTRACT FROM AUTHOR]

Defect inspection of integrated circuits (ICs) solder joints is a long-standing task. This paper proposes a novel IC solder joint inspection method based on the idea of robust principle component analysis (RPCA), which is a celebrated optimization technique. To the best of our knowledge, this is the first time IC solder joint inspection is formulated as an optimization problem. In particular, we model an IC solder joint image as observed data corrupted by gross errors. According to the RPCA theory, the observed data can be approximately decomposed into a low-rank component and an error component. In this paper, an appearance model of qualified IC solder joints is defined for IC solder joint inspection based on RPCA. Then, a defect score is defined based on the appearance model and is used to evaluate the quality of IC solder joints. Meanwhile, location prior knowledge related to human perception is incorporated in the defect score to further evaluate the defects of IC solder joints. Finally, a simple discrimination scheme is proposed to inspect IC solder joints. Experimental results indicate that the proposed method is superior to the existing methods in inspection performance. [ABSTRACT FROM AUTHOR]

Stochastic spectral methods have achieved a great success in the uncertainty quantification of many engineering problems, including variation-aware electronic and photonic design automation. State-of-the-art techniques employ generalized polynomial-chaos expansions and assume that all random parameters are independent or Gaussian correlated. This assumption is rarely true in real applications. How to handle non-Gaussian correlated random parameters is a long-standing and fundamental challenge: It is not clear how to choose basis functions and to perform a projection step in a correlated uncertain parameter space. This paper first presents a new set of basis functions to well capture the impact of non-Gaussian correlated parameters and then proposes an automatic and optimization-based quadrature method to perform projection-based stochastic collocation with a few simulation samples in the correlated parameter space. We further provide some theoretical proofs for the complexity and error bound of our proposed method. The numerical experiments on several synthetic, electronic, and photonic integrated circuit examples show the nearly exponential convergence rate of our approach and its significant ($700 \times $ – $6000 \times $) speedup than Monte Carlo. Many other open problems with non-Gaussian correlated uncertainties can be further solved based on this paper. [ABSTRACT FROM AUTHOR]

Integrated voltage regulators (IVRs) support an increasing number of voltage domains while enhancing the transient response and enabling fine-grained dynamic voltage frequency scaling. A voltage regulator (VR)-on-package is a promising IVR topology, which supports high-voltage transmission within a printed circuit board and package, leading to lower distribution loss. A power delivery network within a VR-on-package environment is presented in this paper. This paper also presents a study of VR top- and bottom-placement topologies within a system-in-package environment in terms of electromagnetic interference (EMI) and power integrity. This comparative analysis targets a specific server package application, and the power integrity evaluation is focused on the power delivery network between the VR and IC. The VR top-placement topology exhibits more than $3\times $ less EMI and 15.3% lower worse case IR drop as compared with the VR bottom-placement topology. The tradeoffs are, however, a greater package power loss and higher package cost due to the larger number of package layers in the VR top-placement topology. The VR top-placement topology exhibits a 52.6% higher power loss through the package than the VR bottom-placement topology. [ABSTRACT FROM AUTHOR]

The reliability of microcontrollers (MCUs) became crucial considering their massive use in numerous applications, especially in severe environments. Thus, the robustness against electromagnetic disturbances, particularly for the power supply network, is a major issue that we have to solve in order to acquire a comparative advantage on the market, or simply to assure the goods and people safety. Therefore, the fast transient burst test of integrated circuits is studied in relation with the IEC 61000-4-4 standard. The stress propagation mechanisms are highlighted, as well as the common-mode -to-differential-mode conversion. A novel measurement method was developed to validate this conversion. Finally, this paper opens new perspectives of improvement of the MCU robustness, such as package modification, for this kind of aggression, and thus their reliability. [ABSTRACT FROM AUTHOR]

As a method of producing radio frequency identification (RFID) tags, printed graphene provides a low-cost and eco-friendly alternative to the etching of aluminum or copper. The high resistivity of graphene, however, sets a challenge for the antenna design. In practice, it has led to using very large antennas in the ultrahigh-frequency (UHF) RFID far-field tags demonstrated before. Using inductive near field as the coupling method between the reader and the tag is an alternative to the radiating far field also at UHF. The read range of such a near-field tag is very short, but on the other hand, the tag is extremely simple and small. In this paper, near-field UHF RFID transponders with screen-printed graphene antennas are presented, and the effect of the dimensions of the tag and the attachment method of the microchip studied. The attachment of the microchip is an important step of the fabrication process of a tag that has its impact on the final cost of a tag. Of the tags demonstrated, even the smallest one with the outer dimensions of 21 mm $\times \,\, 18$ mm and the chip attached with isotropic conductive adhesive (ICA) was readable from a distance of 10 mm with an RF power marginal of 19 dB, which demonstrates that an operational and small graphene-based UHF RFID tag can be fabricated with low-cost industrial processes. [ABSTRACT FROM AUTHOR]

This paper demonstrates an experimental micro- channel solution to cool microelectronic chips with hotspots, using an integrated, yet nonintrusive technique. In microelectronics, approaches such as die thinning induce acute stress on cooling because it increases the hotspot phenomena and reduces chip bulk thickness that could be used for microchannels. In compact devices, heat must be removed using limited pumping power and cooling space. Microchannels etched in the backside of the chip, usually considered as an efficient cooling solution, are impracticable on highly thinned chips. This paper experimentally investigates the cooling performance of a noninvasive and hotspot aware microchannel die that is in direct fluidic contact with the backside of the microelectronic chip. It also proposes a confinement-wise metric. A thermal resistance of 2.8 °C/W is achieved at a heat flux of 812 W/cm2 per heat source, for a total dissipated power of 20 W and a maximum allowed temperature rise of 55 °C. Such performance is obtained with only 19.2 kPa of pressure drop and 9.4 ml/min of flow rate, corresponding to a hydraulic power of only 3 mW and a coefficient of performance of 6500. In addition, the complete chip stack, including the thinned chip, measures only $660~\mu \text{m}$ high. Therefore, backside cooling appears to be a promising compact and low consumption solution for compact electronic applications having confined hotspots. [ABSTRACT FROM AUTHOR]

In this paper, the influence of microwave curing on the reliability of a representative electronic package is examined by reliability testing and measurement of residual stresses. A LM358 voltage regulator die was mounted to an open quad flat no-leads (QFN) package for reliability testing. For the stress measurement, a specifically designed stress measurement die was mounted to the QFN package. The chips were encapsulated with Hysol EO1080 thermosetting polymer material. Curing was performed using an open-ended microwave oven system equipped with in situ temperature control. Three different temperature profiles for microwave curing were selected according to the requested degree of cure and chemical composition of the cured material. A convection cure profile was selected for the control group samples. Temperature cycle tests and highly accelerated stress tests (HAST) were performed on a total number of 80 chips. Ninety-five QFN packages with stress measurement chips were also manufactured. The increased lifetime expectancy of the microwave-cured packaged chips was experimentally demonstrated and measured between the 62% and 149% increased lifetime expectancies after temperature cycle test (TCT), and between 63% and 331% after a HAST and TCT compared to conventionally cured packages. The analysis of specifically designed stress test chips showed significantly lower residual stresses ranging from 26 to 58.3 MPa within the microwave-cured packages compared to conventionally cured packaged chips, which displayed residual stresses ranging from 54 to 80.5 MPa. Therefore, this paper provides additional confidence in the industrial relevance of the microwave curing system and its advantages compared to the traditional convection oven systems. [ABSTRACT FROM AUTHOR]

Plastic-encapsulated packages are known to suffer package stress issues which often cause undesired shifts in the IC electrical parameters. Two types of package stress are analyzed and their contributions to the overall package stress in a Quad-Flat No-leads (QFN) Package are experimentally studied in this paper. The volumetric package stress generated by the mold compound is analyzed using the material properties of the bulk modulus and the volumetric coefficient of thermal expansion (vCTE). The in-plane package stress generated by the die and the die-attach material is analyzed using the structural analysis method with the introduction of an improved Suhir solution to evaluate the in-plane normal stress at the active area of the IC die. These theoretical analysis results are further experimentally studied with the functional measurements on a precision CMOS bandgap voltage reference in a QFN package. Using the combination of two different die-attach methods and two different die-coating conditions, the parametric variations in the bandgap voltage can be correlated with the different types of package stress. The actual test data presented in this paper are in good agreement with the theoretical analysis results. [ABSTRACT FROM AUTHOR]

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded \(in~situ\) sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded \(in~situ\) sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness. [ABSTRACT FROM AUTHOR]

A circuit model for dual-mode resonators is proposed to develop a design procedure that facilitates the design of parallel-coupled dual-mode resonator filters. Based on the design procedure, a parallel-coupled dual-mode resonator filter can be designed in a way similar to the design of parallel-coupled line filters. Compared to the parallel-coupled line filter that uses half-wavelength line resonators, the use of dual-mode resonators not only achieves smaller size and better performance, but does not complicate the design and fabrication processes, as demonstrated in this paper. Accordingly, the parallel-coupled dual-mode resonator filter can be a good candidate for many practical applications that accept the Chebyshev or Butterworth response. [ABSTRACT FROM PUBLISHER]

This paper describes a method and a prototype of an integrated circuit of a temperature-controlled oscillator to address problems with overheating of high-performance processors working under thermal and energy saving constraints. Some theoretical considerations about the method are provided. Structure and measurement results of a circuit designed and fabricated in UMC CMOS 0.18 \mu \textm (1.8 V) are presented. The circuit consists of a set of proportional to absolute temperature sensors, a temperature comparator and maximum temperature detection circuit, a controlled ring oscillator, and additional blocks to manage the processor according to the presented method. The main aim of the circuit is to optimize the processor performance for a specified temperature limit, based on dynamic scaling of the operating frequency. The tuning is continuously and instantaneously performed by a signal from a sensor indicating maximum temperature directly measured in the silicon die. [ABSTRACT FROM AUTHOR]

Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time-consuming for the drop test simulation, and therefore the fast numerical approach is needed to reduce the computational cost. In this paper, we propose an efficient drop test simulator for through-silicon-via (TSV)-based 3-D IC to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second-order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. Second, an equivalent structure-embedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop test simulator can achieve $7.03\times $ speedup in comparison with the conventional finite-element method-based solver. It is demonstrated in this paper through several examples with multichip layers, of which each chip layer consists of an $8\times 8$ TSV array, that the proposed simulator can be widely applied to reliability analysis of 3-D ICs under drop impact. [ABSTRACT FROM AUTHOR]

Full characterization of transmission lines fabricated on printed circuit boards is presented in this paper. For this purpose, the frequency at which the attenuation curves associated with the conductor and dielectric losses cross over is first determined to exactly separate the corresponding contribution to the total attenuation. Afterward, permittivity, loss tangent, effective geometry, and rms roughness are obtained from the propagation constant and characteristic impedance data for allowing the transmission line representation up to 20 GHz. Using the extracted parameters, the excellent model-experiment correlation for the S-parameters of the lines is observed. In fact, the curves of complex-impedance versus frequency are also corrected from undesired resonances typically occurring in experimental data. Finally, it is demonstrated that the extracted parameters allow performing causal time-domain simulations. [ABSTRACT FROM PUBLISHER]

Through silicon via (TSV) is the most promising technology for vertical system integration and novel 3-D chip architectures. Reliability and quality assessment necessary for process development, root-cause analysis, and manufacturing require appropriate nondestructive testing techniques to achieve high processing yield and reliability. This paper presents two advanced approaches for nondestructive localization of defects in TSVs. The first method investigated here was lock-in thermal imaging by thermography and photoemission microscopy to inspect and localize electrical shorts within the 3-D geometry of the TSV insulation liner. In addition, filling defects in the TSVs have been inspected using acoustic microscopy in the gigahertz frequency band in time and spectral domains. [ABSTRACT FROM PUBLISHER]

With the rapid development of the integrated circuit (IC) industry, testing of IC chips is becoming more and more important. A chip probe final test is an important means of final chip testing, which makes use of contacts between probes and bumps on the chip for electrical connections of the test instrument and the chip, through which the electrical characteristics of the chip are tested one by one. The IC final test is directly completed on the entire packaging wafer before the packaging wafer is cut into single die. This complete testing of the whole wafer before dicing can greatly improve the efficiency of the final test. The precise alignment of probe and chip bumps is an important aspect of the final test process. In this paper, image processing is carried out based on the rectangular frame of the chip surface, for which the rectangular box image-processing algorithm is designed. The chip image showing the deflection angle is acquired, and the offset distance is calculated. The rectangular box algorithm based on the principle of the Hough transform detects the orientation that is used to determine the offset of the rectangular frame. The detection accuracy and efficiency of the algorithm is evaluated, and it is shown that the image-processing algorithm of the chip alignment is improved significantly. An efficient automatic probe final test of packaging wafers can finally be achieved. [ABSTRACT FROM PUBLISHER]

This paper presents two filtering Wilkinson power dividers (FWPDs) with high selectivity and miniature size. A multimode resonator is used to replace a quarter-wavelength transmission line in a conventional Wilkinson power divider, and then the resonator-based FWPD is capable of splitting power and selecting frequency simultaneously. Two tri-mode resonators and two quad-mode resonators are applied to design a single- and a dual-band FWPD, respectively. Characteristics of the tri- and quad-mode resonators are analyzed, and the equivalent circuits of the proposed single- and dual-band FWPDs are presented. The input port matching and filtering response are explained by the even-mode equivalent circuit, while the output port matching and isolation characteristics can be investigated by the odd-mode equivalent circuit. Moreover, the magnetic source-load coupling introduces multiple transmission zeros to improve the frequency selectivity. All measured results are in good agreement with the full-wave simulation results. [ABSTRACT FROM PUBLISHER]

Thermoelectric generators (TEGs) can improve the net power consumption of electronic packages by generating power from the chip waste heat. In this paper, a 3-D computational model of electronic package with silicon nanowire (Si-NW)-based embedded TEGs has been developed and the effect of crucial geometric parameters, contact resistances, and thermal properties, such as pitch length and length of Si-NWs, the electrical contact resistivity at Si-NW interface, thermal contact resistivity at TEG-package interface, and filling material thermal conductivity on power generation, has been evaluated. The analysis has shown how modifying some crucial parameters from their current values in different experimental studies affect power generation, e.g., decreasing the pitch length from 400 to 200 nm doubled the power generation, increasing the Si-NW length from 1 to 8 \mu \textm increased power generation by a factor of three and decreasing contact resistivity by one order of magnitude from 1.0\times 10^-11\Omega \,\cdot \,\textm^2 enhanced the power generation by a factor of two. This paper has estimated the energy conversion efficiency of 0.15% for 8- \mu \textm long Si-NWs using the best thermoelectric properties available from different experimental studies. Finally, performance of Si-NW-based TEG has been compared against the Bi2Te3 superlattice-based TEGs and the crucial parameters of Si-NW TEGs have been identified which should be the focus of the future studies. [ABSTRACT FROM AUTHOR]

This paper aims at determining thermomechanical stress variations induced by annealed copper filled through-silicon via (TSV) in single crystalline silicon using metal–oxide–semiconductor (MOS) rosette sensors. These eight branches sensors were specifically designed and embedded in a 65-nm CMOS technology test vehicle. An in-house four-point bending tool was employed to calibrate and to extract the six independent piezoresistive coefficients. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on wafer splits. A finite-element approach was also adopted to evaluate numerically the stresses and the expected mobility variations induced by TSV. According to this paper, a large variation of stresses (up to 100 MPa) in the sensor area was estimated, suggesting possible sensor design improvements to better accuracy. A good agreement was obtained between numerical and experimental results, except for the orthoradial component, which was found slightly compressive experimentally. Based on a critical analysis of the experimental–numerical methodology and results detailed in this paper, guidelines are drawn to get better accuracy through the improvement of MOS size and positions as well as recommendations regarding test strategy to overcome process variability. In the longer term, such improvements should lead to the definition of a comprehensive strategy for mechanical stress probing with in situ structures in advanced semiconductor products. [ABSTRACT FROM AUTHOR]

This paper presents novel linearly polarized (LP) and circularly polarized (CP) patch antennas for wideband wireless devices. Advanced electrical characteristics of the antennas including wide bandwidth, low cross polarization, low back radiation, and polarization insensitivity contribute to improve the signal quality of wireless connectivity. It is a realization of antenna foundation by employing multilayer microwave laminates to form a substrate integrated meandering probe-fed patch antenna. First, a design and analysis of the proposed patch antenna for LP operation is carried out. Based on the obtained results of this LP element, a substrate integrated meandering probe fed CP patch antenna is exhibited afterward. This paper is considered as a part of RF modules that could be integrated with other components like sensors, Microcontroller units, and electronic parts to form a wireless product by means of conventional packaging process. [ABSTRACT FROM AUTHOR]

This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a novel stacking structure that eases the thermal problem. The objective of this paper is first to define limits and opportunities for developing different 3-D chip stacks from a thermal perspective, and second to explore our proposed system as a function of microbumps, through silicon vias, die thickness, and other design parameters. In our proposed 3-D stack, the interposer integrated microfluidic heat sink serves as the main heat sink. To thermally decouple stacked dice, we propose air gap isolation between them and a thermal bridge on top of the stack to cool down the isolated die. To evaluate the thermal benefits of the stack, a thermal model is developed based on the finite difference method. Several chip stack scenarios are studied and the simulations are conducted with a processor power of 74.63 W/ \mathrmcm^2\vphantom \Big ( and memory power of 2.82 W/ \mathrmcm^2 . The proposed architecture yielded processor and memory temperatures of 64 °C and 40 °C, respectively, compared with 76 °C and 75 °C for the air cooled stack. [ABSTRACT FROM PUBLISHER]

To speed up the object location for the IC packaging inspection, this paper develops a novel binary large object (BLOB) analysis algorithm by using run length encoding (RLE). First, the new data structures for RLE and BLOB-linked lists are designed to accelerate the access and modifications of data. Second, to avoid the traditional labeling conflicts and simplify the comparisons of connectivity branches, an efficient algorithm for BLOB analysis is presented. Furthermore, area feature of objects can be extracted when the BLOB-linked list are dynamically created or modified. Finally, to evaluate the performance of the proposed method, ICs with various types of small outline packaging packages were located by the proposed algorithm. The experimental results not only demonstrate that the IC pins could be effectively and robustly located with the proposed algorithm, but also show that the presented algorithm runs faster than other classical methods. [ABSTRACT FROM AUTHOR]

Integrated circuit (IC) package assembly and test processes include several industrial steps involving physical contact and/or friction between polymer surfaces of handlers and packages. The trend toward smaller and sleeker gadgets has resulted in a dramatic reduction in the package weight due to thickness and size miniaturization. In this paper, we show that the forces created through triboelectrostatic charging between surfaces of handlers and packages are comparable with the weight of thin and small IC packages. Furthermore, the voltages generated in such triboelectric interactions are rather small—typically below the concern levels set in the IC industry. The results show that for IC packages with a subgram weight, the impact of the triboelectrostatic force on the assembly processes is significant and occurs at low static voltages (<200~V) . The data presented in this paper provides valuable insights into the selection of materials for handler designs in contact with IC packages during assembly and test processes. [ABSTRACT FROM AUTHOR]

This paper presents a technique to perform steady-state simulation of optical–electrical systems using the harmonic balance (HB). One of the unique features of this method is that it includes the phase of the optical signal in finding the steady-state solution of the system. The inclusion of phase in a framework using HB poses several challenges since all system variables in HB are assumed to be periodic, whereas the phase of optical signals is, in general, nonperiodic, owing to the nonzero chirp present in laser diodes that are used as drivers for the optical systems. Several examples are presented that demonstrate the feasibility of the proposed method, and, where possible, the results are compared with theory and existing techniques. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology for scalable modeling of IC packages by lumped element equivalent circuits. The response surface methodology is used for modeling of the IC package pins, lead frame, and bond wires, whereas the paddle is modeled as a pair of planes. The design of experiment (DOE) approach is used to systematically vary geometrical parameters of the simplified package structures, which are then simulated in a 3-D electromagnetic (EM) simulator. These simplified structures are used as building blocks of the IC packages and EM simulations of the simplified structures are used to build their parameterized equivalent circuit models. The extracted parameters of the equivalent circuit model form the response surface. Simple regression models are used for the response surface modeling. The model of the whole IC package is generated by cascading the models of the simplified structures. The range of the geometrical parameters used in the DOE is selected to cover a wide range of IC package geometries. The response surface models are verified against measurements performed on several IC package types and the accuracy is very good. The scalability and accuracy of the response surface models make this methodology suitable for modeling of a wide range of IC packages. The efficiency and accuracy of the presented models enable the statistical analysis of package performance with respect to package manufacturing parameters. [ABSTRACT FROM AUTHOR]

This paper presents design, experimental characterization, and feasibility analysis of integrated in-package fluidic cooling for mobile systems-on-chips (SoCs). A pin fin interposer for fluidic cooling is designed and integrated with a commercial SoC. The demonstrated system integrates an active low-power piezoelectric pump controlled by the SoC itself and a metal/acrylic-based board-scale heat spreader and exchanger. Different software-based policies in the SoC for controlling the fluid flow based on SoC’s temperature and performance are implemented and compared. The measurement results demonstrate that the in-package fluidic cooling improves the SoC’s energy efficiency and reduces design footprint compared to external passive cooling. [ABSTRACT FROM AUTHOR]

Conventional model-order reduction techniques used in circuit simulation guarantee the passivity and, consequently, the stability of the reduced circuit provided that the original circuit is passive. This excludes a large class of circuits that are stable but not necessarily passive. In this paper, an algorithm is described that guarantees the stability of the reduced circuit by construction. Numerical examples are presented that validate the efficiency and accuracy of the proposed method. [ABSTRACT FROM PUBLISHER]

A waferlevel package (WLP) that has a flipchip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure- and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure–volume–temperature–cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry- and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation. [ABSTRACT FROM PUBLISHER]

With the increasing demands of radio-frequency identification (RFID) applications, an alternative ink-jet printing technique for RFID tag antenna is demonstrated. Commercially available ink-jet printers are adapted for conductive printing, in order to minimize manufacturing cost. Paper-based dipole antenna and dipole with a tuning stub antenna were designed. The antennas were ink-jet printed and assembled with RFID chips. The performances of the fabricated tags were measured through the reading range. With reference to equivalent isotropically radiated power of 4 W at 923 MHz, the reading range of tag with dipole antenna is around 9 m and of tag with dipole with a tuning stub is nearly 13 m. These performances are comparable to those of commercial tags. The advantages of the proposed printing technique are simplicity, flexibility and, more importantly, affordability. The technique can, in addition, contribute to further development and enhance extension of RFID applications. [ABSTRACT FROM PUBLISHER]

Thermal control of printed circuit board and integrated circuit package is challenging in microelectronics because the power density increases when smaller and more complicated packages are designed. Temperature rising due to power dissipation and hotspots worsens harmful clock skew and jeopardizes reliability of products. To overcome these risks, designers have to perform electromagnetic-thermal co-simulations at the early design stage. However, it is difficult to detect the hotspots in the package because very high-resolution simulations are needed. In this paper, an improved adaptive finite element method (FEM) is applied to detect hotspots, which only needs one-step adaptive refinement for a given error threshold, which is very fast and uses much smaller computation resources. Furthermore, instead of electromagnetic-thermal co-simulation, this method directly finds potential hotspots based on the volumetric heat generation. Test results show that the adaptive FEM only takes about 60 times the memory and CPU time to detect all hotspots when compared to the initial FEM solution. [ABSTRACT FROM AUTHOR]

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (\mu-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <50∼\mum at the outermost region of the packaging structure without \mu-bumps significantly reduces approximately 2 \mum of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF. [ABSTRACT FROM AUTHOR]

Evaluating the robustness of integrated circuits (ICs) against noise and disturbances is of crucial importance in signal integrity (SI) applications. In this paper, the addressed challenge is to build a software-based framework allowing for automated detection of failures and fast simulation-based evaluation of designs. In particular, these tasks are here addressed using anomaly detection (AD), a branch of machine learning (ML) techniques focused on identifying erroneous or deviant data. In the proposed framework, the ML model only requires the time-domain waveforms and no additional knowledge about the circuit nor about the errors to be identified. Specifically, a two-step approach to detect anomalous behaviors in output waveforms of digital ICs is proposed, comprising a first phase where the ML models are trained to learn relevant features describing the data and a second one where those features are used to identify anomalies with unsupervised or semisupervised AD techniques. Two relevant application examples validate the performance and flexibility of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

In this paper, over a broad frequency band, a novel transmission line (TL) characterization method for highly-lossy miniaturized integrated circuit (IC) interconnect lines is presented. TLs fabricated on lossy organic substrates are difficult to characterize in a broad frequency band due to frequency-dependent losses and resonances. Test TLs are fabricated using a packaging process that employs an organic substrate and then characterized by using a vector network analyzer up to 40 GHz. TLs are modeled as a function of frequency by combining the modified skin effect model with experimental S-parameter data. Parallel admittance of TLs can be yielded by unifying the propagation constant with the frequency-variant resistance and inductance models, followed by TL characterization. It is verified that IC package interconnect lines can be reliably characterized up to high frequencies. [ABSTRACT FROM AUTHOR]

Nowadays, thinner and slimmer smartphones have been widely applied in daily life. In most portable devices, liquid-crystal display driver integrated circuit (IC) or new touch display driver IC are critical components, in which the gold bumping process is used as an essential interconnection technology and usually outsources to out-sourced assembly and testing factories. In semiconductor packaging manufacturing, due to popular high-definition requirements of display devices, gold bumping processes require very low fraction of nonconformities. For this reason, accurately evaluating the manufacturing yield is very important to guarantee the quality requirements being met. To evaluate the yield of gold bumping processes, the most popular yield index $C_{\textrm {pk}} $ is widely employed in outsourcing contract arrangements. However, the typical existing nature estimator is a biased estimator and more conservative. In this paper, we provide an unbiased estimator to evaluate the gold bumping manufacturing yield more accurately. Based on the new estimator, we further propose a weighted parametric bootstrap method to obtain a reliable lower confidence bound that is closer to the true manufacturing yield. The new yield assessment can avoid underestimating the gold bumping manufacturing yield and can make more reliable decisions. [ABSTRACT FROM AUTHOR]

To investigate the thermal behavior of 3-D integrated circuits, long computational times are required for large-scale stacked chips with a complicated structure. In this paper, an equivalent anisotropic thermal model is introduced to reduce the computational time resulting from complicated numerical integration. By introducing the equivalent model, the complex nature of the through-silicon via (TSV) structure can be overcome. Our algorithm not only considers the anisotropic structure of the TSV and the orientation of the heat flux, but also considers the influence of the thermal coupling between TSVs. The finite-element method solver COMSOL is used for comparison with the proposed model, revealing a good agreement between the results of the simulation and the proposed models. The maximum deviation is less than 5%, indicating the accuracy of the proposed model, and the computational time of our model is reduced by 95.5%. In addition, parametric studies and studies of the structure are performed in order to further verify the accuracy of the proposed method and understand the main factors affecting the thermal behavior of a stacked 3-D chip. [ABSTRACT FROM AUTHOR]

The shielded-pair through-silicon vias (SPTSVs) proposed in this paper feature superior transmission properties and high jamming immunity suitable for differential-mode and common-mode transmissions. Based on the recursive approximation algorithm, a novel and efficient method for characterizing the electromagnetic-temperature distribution in dielectrics is proposed for SPTSVs. In addition, considering the proximity effects and eddy current effect in substrate, the ultrabroadband parasitic admittance and electrical coupling models are derived based on 2-D time-varying field and transient polarization mechanism. The collaborative finite-element analysis shows that the proposed model highly agrees with the 3-D full-wave simulation (HFSS 14.0 and Maxwell v16) and the analytical calculation. Then, the dielectric relaxation properties for substrate and oxide are deeply characterized with different design parameters. Finally, the impacts of the substrate effect on electrical characteristics of SPTSVs are revealed. [ABSTRACT FROM AUTHOR]

Modern power electronics has the increased demands in current density and high-temperature reliability. However, these performance factors are limited due to the die attach materials used to affix power dies microchips to electric circuitry. Although several die attach materials and methods exist, nanosilver sintering technology has received much attention in attaching power dies due to its superior high-temperature reliability. This paper investigated the sintering properties of nanosilver film in double-side sintered power packages. X-ray diffraction results revealed that the size of nanosilver particles increased after pressure-free sintering. Compared with the pressure-free sintered nanosilver particles, the 5-MPa sintered particles showed a higher density. When increasing sintering pressure from 5 to 30 MPa, the shear strength of the sintered package increased from 8.71 to 86.26 MPa. When sintering at pressures below 20 MPa, the fracture areas are mainly located between the sintered Ag layer and the surface metallization layer on the fast recovery diode (FRD) die. The fracture occurs through the FRD die and the metallization layer on the bottom molybdenum substrate when sintering at 30 MPa. [ABSTRACT FROM AUTHOR]

One of the main difficulties that prevent the use of integrated circuits (ICs) with ball grid array packages in space is the early fatigue of their solder joints. Early solder fatigue originates in the thermomechanical stress cycles produced by the different coefficients of thermal expansion (CTEs) of the printed circuit board and the IC package and the temperature fluctuations that they suffer during a space mission. In this paper, we propose an active cancellation mechanism to extend the lifetime of the solder joints with minimum energy consumption and show the simulation results from its modeling. [ABSTRACT FROM AUTHOR]

Flow rate nonuniformities (termed as maldistribution) among a stack of microchannels connected with each other through the inlet/outlet plenums of a microchannel heat sink (MCHS) are one of the major hindrances associated with effective and efficient operations. That induces many undesirable effects, including accentuation of lateral and flow direction nonuniformities in surface temperatures (for uniform heat flux loads). This can lead to feedback-induced lateral heat flow in the electronics underneath the MCHS, which is to be avoided. For the reported numerical study of single-phase liquid cooling, a new flow maldistribution mitigation technique—involving splitting of the single inlet port to the inlet manifold (conventional) into two separate inlet ports—is proposed, and the results are compared with the conventional method. The proposed scheme helps in reducing the flow maldistribution (its measure defined in this paper) problem. In the case of two ports, in the front of the inlet manifold, the reduction is about 26.2%, and in the case of one suitably placed port on each side of the inlet manifold, the flow rate maldistribution is reduced by about 68.5%, and in addition, the MCHS efficiency (defined as heat-carrying capacity per unit pumping power) is improved by 7.7%. [ABSTRACT FROM AUTHOR]

Nonconductive films (NCFs) have been introduced for 3-D through-silicon via chip stacking interconnection using reliable fine pitch Cu-pillar/Ni/SnAg microbumps. In this paper, four NCF materials with various elastic modulus and coefficient of thermal expansion (CTE) values were used to investigate the effect of the thermomechanical properties of the NCFs on the thermal cycle reliability of fine pitch Cu-pillar/Ni/SnAg/Cu-pad interconnections. The NCFs’ materials properties were adjusted by changing the ratio of epoxy resins and the curing accelerators. Compared with the borate curing accelerator, the use of the imidazole curing accelerator resulted in better thermomechanical properties on NCFs. And, NCFs containing higher ratio of solid epoxy resins showed higher elastic modulus and higher Tg values when using imidazole curing accelerator. After thermocompression bonding using four different types of NCFs, a thermal cycle reliability test (−40 °C–125 °C) was performed to investigate the effects of the NCFs’ thermomechanical properties on the reliability of Cu-pillar/Ni/SnAg/Cu-pad joints. Due to the CTE mismatch of chips and printed circuit board (PCB) substrates, the SnAg solder joint interconnections were damaged during the thermal cycling. Compared with the four types of NCFs, NCFs with higher elastic modulus at 30 °C showed better thermal cycle reliability. And among the NCFs with similar CTE values, those with higher Tg and higher elastic modulus at 30 °C value showed better thermal cycle reliability. In summary, the NCFs with lower CTE and higher elastic modulus at 30 °C were suitable for highly thermal cycle reliable Cu-pillar/Ni/SnAg/Cu-pad bump joints. [ABSTRACT FROM AUTHOR]