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This paper presents a new approach for the generation of reduced-order compact macromodels of analog circuit blocks (CBs) in highly integrated radio frequency and analog/mixed-signal design. The circuits under investigation are designed and assumed to operate at certain bias points, where they should perform as linear as possible. Therefore, they can be well approximated to first order by linearized transfer function models, assuming small-signal excitation around these operating points. This paper concentrates on a number of key aspects. First, a fully parameterized macromodeling flow is described, for the closed-form inclusion of external geometrical or design parameters in the macromodel responses. This aspect is important for fast optimization, design centering, and what-if analyses. Second, a parameterized DC correction strategy is presented, to guarantee that the DC response of the linearized macromodel matches to machine precision the true DC responses of the original CB. This aspect is fundamental when the macromodel is used in a system-level simulation deck that combines linearized and fully nonlinear models of other components. The main result of proposed approach is a SPICE-compatible reduced-order macromodel that can replace complex transistor-level CBs plus passive interconnect networks, thus enabling dramatic speedup in transient system-level analyses and signal integrity verifications. [ABSTRACT FROM AUTHOR]

This paper presents and discusses results of analysis from investigations of arc-to-glow transformation phenomenon at contact opening, under dc low-energy ( $\leq 10$ J) and low-voltage ( $\leq 250$ V) inductive loads. Dependence of the duration of arcing and glowing on current magnitude, voltage magnitude, properties of the contact material, gas quenching medium velocity and its pressure, as well as contact opening velocity and contact gap are investigated. The transition phenomenon of arc-to-glow is analyzed by means of fast photography and emission spectroscopy. Also discussed is the theoretical evaluation of conditions of arc instability. From the results, possible procedures are formulated to control the arc-to-glow transformation for practical use in dc low-voltage and low-power electrical grids. [ABSTRACT FROM AUTHOR]

Electrical lifespan prediction is one of the key problems for the designers of switching apparatus. It is of great necessity to develop empirical correlations between the design parameters and the electrical lifespan. In this paper, a novel method using the arc erosion mass as the prediction variable is proposed to predict the electrical lifespan of high-voltage direct-current (HVDC) relays. The arc current waveforms are measured, and the arc erosion mass during each breaking operation is calculated based on the relationship between the arc current and the arc erosion rate. The arc erosion mass is accumulated until it reaches a threshold value, which is determined by the electrical lifespan experimental results using HVDC products. It is found that the arc erosion mass linearly accumulates with the lifespan, which is very convenient in the electrical lifespan prediction. Experiments are carried out with a parameter-adjustable device similar to the actual HVDC relay structure. Effects of two key design parameters, the arc-blowing magnetic field flux density and the contact breaking speed, of the electrical lifespan are investigated. The magnetic field flux density is changed in the range from 40 to 80 mT, and the breaking speed is varied from 0.85 to 1.3 m/s. The relationships between the lifespan and the magnetic field flux density as well as the breaking speed are regressively constructed. It is shown that the developed relationships can be used for HVDC relay electrical lifespan prediction. [ABSTRACT FROM PUBLISHER]

This paper investigates the performance and reliability of microcontacts under low-frequency and low-amplitude ac test conditions. Current microcontact theory is based on dc tests adapted to RF applications. To help better apply dc theory to RF applications, frequencies between 100 Hz to 100 kHz were experimentally investigated. Microcontacts designed to conduct performance and reliability measurements were used, which in prior dc testing typically lasted for 100 million cycles or more. Under ac loads, at similar power levels, eight devices were tested under cold-switching conditions, and only one was still operational at 10 million cycles. The effect of external circuitry on dc loaded devices was also considered. The experimental data were presented for dc conditions, which demonstrated that both a parallel capacitance with a microcontact and a series inductance were highly detrimental. For all six tested devices, failure occurred typically in 100 thousand cycles or less. However, utilizing series resistive/capacitive circuits as well as parallel resistor/inductive resulted in improved performance, with only one device of the four tested failing prematurely, but those that lasted showed less variation in measure contact resistance throughout the lifetime of the device. Two devices were tested with passive contact protection using parallel and series resistances, and both devices lasted for the full test duration. Finally, the effects of applying circuit protection to microcontacts and repeating ac test conditions were investigated. Reliability and device lifetime were extended significantly (9.1% success rate without protection was increased to 87% success rate). It was also observed in several instances that devices that failed showed subtle signs of variance during contact closure measurements in the range of 5–30 $\mu$ N, indicating a possible means for accurately predicting device failure. For these failed devices, notable physical damage was observed using a scanning electron microscope. [ABSTRACT FROM PUBLISHER]

3-D integration using through-silicon-vias (TSVs) is emerging as one of the key technology options for continued miniaturization. However, because of increased device and current density, the reliability of the 3-D power grid and its integrity must be studied and analyzed. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. Current densities at these connections can be much higher than the expected average values, so extra care is required for accurate analysis. In prior work, TSVs are modeled as single resistors along with power grid wire segments. Such models do not capture detailed current density distribution and may miss hotspots associated with current crowding. This paper studies current crowding and its impact on 3-D power grid integrity. First, we explore the current density distribution within a TSV and its connections to the global chip power grid. Second, we implement simple TSV models to obtain current density distributions within a TSV and its local environment. These models are checked for accuracy by comparing with models simulated using finite element modeling methods. Finally, the simple TSV models are integrated with the global power grid for detailed chip-scale power analysis. [ABSTRACT FROM PUBLISHER]

Break operations of AgSnO2 contact pairs were conducted in dc inductive (L = 5.7 mH) and resistive load circuits at 14 V and up to around 10 A under different contact opening speeds from 0.5 to 200 mm/s and with/without external magnetic field application in air. Break arc voltage waveforms were observed, and total break arc durations and metallic phase durations were determined based on the observed arc voltage waveforms. After the experiments, averages for total arc durations as well as the metallic phase and gaseous phase (when observed) durations were calculated at each condition. The results show that increases in the contact opening speeds lead to reductions in metallic phase durations, while the application of external magnetic field causes gaseous phases to become shorter. [ABSTRACT FROM PUBLISHER]

This paper illustrates the performance evaluation methods for bidirectional optoelectronic circuit boards (OECBs) operating at 10 Gb/s. A typical OECB consists of flip chip surface mount optical transceiver modules and polymer optical interconnects. The evaluation techniques include direct current and high-speed optical characterizations of individual components, subsystems, and interconnect. A methodical procedure to validate optical waveguide, vertical cavity surface emitting laser, photodiode, high-speed optical characterization of transmitter, receiver, and optical link is described. [ABSTRACT FROM PUBLISHER]

For accurate DC IR-drop analysis of integrated circuits, electrical-thermal co-simulation is necessary to consider the effect of Joule heating. A suitable numerical method for this co-simulation is the finite element method (FEM) because of its capabilities in modeling complex geometries and materials. To deal with large-scale problems, a domain decomposition scheme is applied to the FEM to enable simulation with multiple processors in parallel and achieve significant reduction in computation time. [ABSTRACT FROM AUTHOR]

Printed conductive traces on flexible substrates offer many potential applications in the area of wearable electronics, ranging from search and rescue operations to health and physiological monitoring. The literature abounds on the effect of sintering conditions on the dc electrical resistivity of printed traces, due to the applications considered which fall in the lower frequency domain (megahertz range). There is a growing interest to investigate wireless body area networks for wearable electronics operating in the higher frequencies, due to the advantages involved. At present, there is a little information available on the radio frequency performance of printed interconnects, and this work seeks to investigate the effect of the paste property on the dc conductivity and high-frequency performance ( $\le 30$ GHz) of interconnects. The results obtained suggest that paste leveling has a significant influence on the dc electrical performance. In addition, the dc conductivity values are possibly affected by the adhesion of the paste onto the particular substrate during the printing process, which was observed to have a significant effect on the quality and thicknesses of the traces printed. Last, the influence of the dc conductivity on the high-frequency performance of interconnects is investigated, where the measured results are validated with simulation results. [ABSTRACT FROM PUBLISHER]

Insulation resistance (IR) degradation in Ni–BaTiO3 multilayer ceramic capacitors has been characterized by the measurement of both time to failure (TTF) and direct current leakage as a function of stress time under highly accelerated life test conditions. The measured leakage current-time dependence data fit well to an exponential form, and a characteristic growth time \tau SD can be determined. A greater value of \tau SD represents a slower IR degradation process. Oxygen vacancy migration and localization at the grain boundary region results in the reduction of the Schottky barrier height and has been found to be the main reason for IR degradation in Ni–BaTiO3 capacitors. The reduction of barrier height as a function of time follows an exponential relation of \phi ( t )=\phi (0)e^-2Kt , where the degradation rate constant K=K0e^{(-{Ek}/{kT})} is inversely proportional to the mean TTF (MTTF) and can be determined using an Arrhenius plot. For oxygen vacancy electromigration, a lower barrier height $\phi (0)$ will favor a slow IR degradation process, but a lower $ \phi (0)$ will also promote electronic carrier conduction across the barrier and decrease the IR. As a result, a moderate barrier height $ \phi (0)$ (and therefore a moderate IR value) with a longer MTTF (smaller degradation rate constant $K$ ) will result in a minimized IR degradation process and the most improved reliability in Ni–BaTiO3 multilayer ceramic capacitors. [ABSTRACT FROM AUTHOR]

A multilayer organic package with embedded 60-GHz antennas and fully integrated with a 60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes sixteen phased-array antennas, an open cavity for housing the flip-chip attached RF chip, and interconnects operating at DC–66 GHz. The 28 mm \times\,28 mm ball grid array package is manufactured using printed circuit board processes and uses a combination of liquid-crystal polymer and glass-reinforced laminates, allowing excellent 60-GHz interconnect and antenna performance. The measured return loss and gain of each antenna from 56 to 66 GHz are \sim10∼dB and \sim5∼dBi, respectively. Finally, the packaged transmitter and receiver chipsets, each working with a heat sink, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s using 16-quadrature amplitude modulation single-carrier and orthogonal frequency division multiplexing schemes. [ABSTRACT FROM AUTHOR]

Contour integral method, well-known for the analysis of 2-D full-wave effects on power planes, is extended here for the computation of DC resistances of power planes. In particular, circular elements, e.g., vias and antipad holes, are treated using cylindrical modal expansion functions, which leads to a more efficient and accurate calculation than the conventional implementation by the linear discretization. For individual power planes, the method produces a resistor network consisting of only the nodes that are associated with power or ground vias, which can be further employed to formulate solutions for complete multilayer structures. The method is applied to several power plane configurations and results are validated by a 3-D finite element method solver. The efficiency of the extended method is analyzed and a reduction of the number of unknowns by a factor of four for the circular elements can be expected by the modal expansion. Good accuracy can be achieved by including up to the second higher order mode for dense clusters of antipad holes. [ABSTRACT FROM AUTHOR]