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In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented. The methodology is proven to be applicable to analyze the temperature evolution of real devices. A low-power package configuration with two different power dissipation scenarios, hotspot (HS) in the corner and HS in the center of the active region, has been considered for the validation. In this way, the importance of the package thermal impact on the definition of the final temperature profiles is highlighted. The error between the measurement and the FTM results remains always below 2.3 °C/W. Moreover, the model has been validated with respect to case studies concerning duty cycles of different durations. This proves the applicability of the model in defining the allowed duration of the chip activity before a maximum threshold temperature is reached. Finally, in this paper, the possibility to use a variable time-step approach in the transient FTM is presented together with the option of computing the temperature in individual points only. This is possible maintaining the same accuracy as if the fully resolved temperature maps would be calculated. [ABSTRACT FROM AUTHOR]

This paper introduces a fully automated greedy algorithm for the construction of parameterized behavioral models of electromagnetic structures, targeting at the same time uniform model stability and passivity. The proposed algorithm is able to determine a small set of parameter configurations for which an external solver provides on-the-fly the sampled scattering parameters of the structure over a predetermined frequency band. These samples are subjected to a multivariate rational/polynomial fitting process, which iteratively leads to a parameterized descriptor realization of the model. The main novel contribution in this paper is the adoption of a model-based approach for the adaptive augmentation of an initially small set of frequency responses, each corresponding to a randomly selected parameter configuration. In particular, the locations of the in-band passivity violations of intermediate macromodels constructed at each iteration are used as a proxy for the model-data error in those regions where input data are not available. This physics-based consistency check, which is enabled by recent developments in multivariate passivity characterization based on Skew-Hamiltonian–Hamiltonian (SHH) spectra, is combined with standard space exploration metrics to obtain a small-size and automatically determined distribution of points in the parameter space, leading to the construction of an accurate macromodel with a very limited number of external field solver runs. The embedded passivity check and enforcement process guarantees that either the final model is passive throughout the parameter space or the residual violations, if present, are negligible for practical purposes. Several examples validate the proposed approach for up to three concurrent parameters. [ABSTRACT FROM AUTHOR]

To investigate and quantify the radiation emission of an electronic package model, the partial element equivalent circuit method combined with the field equivalence principle is developed in this paper and used for the near-field radiation prediction. Furthermore, this paper presents a novel electromagnetic bandgap (EBG) design to suppress the electromagnetic radiation. The simulation results obtained by the proposed method have been validated against the measurement; moreover, the simulation and measurement results demonstrate the noise suppression ability of the new designed EBG structure, which can be used to reduce the electromagnetic radiation of the package. [ABSTRACT FROM AUTHOR]

Through-silicon-via (TSV) technology permits devices to be placed in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to its many advantages. However, there are some challenges for TSV wafer processes. One of the challenges is TSV wafer thinning process (WTP). In this paper, a dynamic finite element modeling methodology was established and used to study the TSV WTP-induced wafer stress. It was found that wafer surface roughness, TSV wafer thickness, bonding/debonding material, and TSV feature size have impact on TSV wafer stress under the TSV WTP. The impact of wafer thinning-induced stress on mobility change was also discussed in this paper. [ABSTRACT FROM AUTHOR]

The 3-D integrated circuits (3-D ICs) are emerging as a viable solution to enhance the performance of many-core platforms. These architectures generate a high and rapidly changing thermal flux that makes conventional air-cooled devices more susceptible to overheating. Liquid cooling is an alternative that can improve dissipation and reduce thermal issues. Fast and accurate thermal models are needed to appropriately dimension the cooling system at design time. Several models have been proposed to study different designs, but generally with low simulation performance. In this paper, we present an efficient model of the transient thermal behavior of liquid-cooled 3-D ICs. This paper presents an approach with extremely low memory usage and advanced numerical methods to efficiently compute the transient temperature of 3-D ICs. Our experiments show the $100\times $ speedup versus the state-of-the-art models, while maintaining the same level of accuracy, and demonstrate the efficiency of liquid cooling to remove the heat from 3-D many-core platforms. [ABSTRACT FROM PUBLISHER]

This paper addresses the problem of fast transient simulation of high-speed coupled channels driven by transceivers that include transmitter feed-forward equalization (TX-FFE). Practical circuit hardware implementations of such drivers may not be correctly represented by industry-standard algorithmic modeling interfaces (AMIs), which are usually based on ideal digital finite impulse response filters. In particular, slow transients may arise when aggressive FFE is activated and particular switching sequences significantly stress local voltage regulators integrated in the output buffers. In this paper, we model this effect using a constructive hierarchical approximation of the analog waveforms that form a linearized vector Thevenin or Norton representation of the driver. This representation enables the accurate simulation of coupled channels including both differential- and common-mode signals. Analog waveforms at the receiver input are readily obtained by standard time-frequency transformations while including channel characteristics and any additional linear equalization block, if present. This proposed framework is compatible with industry-standard AMIs, extending their scope to coupled channels with nonideal TX-FFE circuit blocks. Eye diagrams and transient waveforms corresponding to millions of bits are computed in few seconds using a nonoptimized software implementation. Random jitter and crosstalk are seemlessly included as in standard AMI frameworks. The results of various numerical experiments on commercial transceivers are reported in this paper, confirming both the accuracy and the efficiency of the proposed framework. [ABSTRACT FROM AUTHOR]

This paper presents methods for the modeling of the localized (near) fields of vertical interconnects in silicon interposers and the applications of these methods for the efficient computation of the electromagnetic properties of through silicon via structures. The localized fields are due to the mode conversions of the coaxial-to-radial waveguide junctions present in these structures. Because exact analytical techniques exist only for the homogeneously filled junction, an efficient numerical technique is proposed in this paper for the modeling of the inhomogeneous cases. This technique provides accurate results in the form of network parameters with three ports, which can be applied, e.g., in the framework of the physics-based via models. The finite-difference frequency domain method for the case of rotational symmetry is adapted to variable grid distances along the axial and radial coordinates, and interface conditions for the inhomogeneous filling of silicon and electrically isolating silicon dioxide are implemented. The method is validated with full-wave results from finite-element simulations and with the results from the published analytical methods that are adapted to the layered structures. The main focus is in the modeling for signal integrity analysis from the frequencies where the skin effect is well developed at about 100 MHz up to 100 GHz. Nevertheless, good agreement with the results from finite-element simulations up to 500 GHz is obtained for several relevant example structures, and a speedup of at least two orders compared with the finite-element simulations is achieved. [ABSTRACT FROM AUTHOR]

Board-level simulation has to consider, at the earliest stage of the conception, the impact of the vicinity of numerous high- and medium-powered devices. In 1996, the European consortium DELPHI defined the concept of a surrogate, or compact thermal model (CTM), to minimize the computation times from days to minutes. A DELPHI-style CTM resumes an electronic component as a simple cuboid form and a network of resistors that links a single temperature-sensitive node to the major surfaces of heat extraction. That steady-state network is derived from a detailed numerical model, which is subjected to a set of boundary conditions (BCs) applied on its external surfaces. At first, this paper investigates the combinations of various sets of scenarios to generate and to test a multiport surrogate model. The objective is to define the lowest number of numerical simulations required while keeping the highest accuracy level of the derived BC-independent (BCI) thermal network. Then, this paper demonstrates the need of a smart selection of the isothermal surfaces to create a most relevant surrogate model. Finally, using that calibrated steady-state model, an extension of the DELPHI method to create multiport dynamic surrogate model is proposed as well as a set of BCs dedicated to transient network fitting. [ABSTRACT FROM AUTHOR]

Switchgear is an important power system protection equipment. Internal overheating of high-current switchgear has become the most common problem in the power system. In this paper, two different methods of simulation model are adopted to study the temperature rise issues of the 12-kV medium voltage switchgear. First, the electromagnetic field is calculated by using ANSYS APDL, then coupling with fluid dynamics software CFX to give the temperature and flow field distribution of the switchgear. Second, FLUENT and Maxwell 3-D are used to get the temperature and flow field distribution. It can be proven that CFX simulation of flow field is more suitable for the complex models. In the meantime, it has huge differences with FLUENT software when the temperature rise of the switchgear is calculated. In this paper, the influences of inlet velocity, the number of ventilation holes, and their positions are further studied, which could provide theoretical guidance for reducing temperature rise of the switchgear. [ABSTRACT FROM PUBLISHER]

The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D integrated circuits (ICs). Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multiscale strategy, whose core is constituted by a highly resolved, convolution-based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time-dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite-element method results shows good accuracy. An error metric, to estimate a priori the need to include the package impact on top of the convolution-based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this paper. [ABSTRACT FROM AUTHOR]

With continued technology scaling and increased power and thermal densities, processor operation and performance are increasingly dominated by physical phenomena. Microarchitectural approaches to mitigate these effects must be based on a profound understanding of how the physics is manifested in microarchitectural executions and system-level properties, such as performance, energy efficiency, or lifetime reliability. This requires a modeling and simulation environment that incorporates multiple physical phenomena and their concurrent interactions with microarchitecture. In this paper, we introduce an integrated power, thermal, and reliability modeling framework, KitFox. The goal of KitFox framework is to facilitate research explorations at the intersection of applications, microarchitectures, and various physical phenomena, including energy, power, thermal, cooling, and reliability. The KitFox framework implements a standard interface to bridge multiple physical models, where individual models are encapsulated into libraries and are interchangeable. This paper describes the design methodology of the library framework that orchestrates various implementations of physical models and standardized interface to cycle-level microarchitecture simulators. Several use cases are presented to demonstrate the range of modeling capabilities of KitFox. [ABSTRACT FROM PUBLISHER]

Handheld electronic devices are subject to mechanical shocks, which is one of the primary sources of failures. When a device is dropped onto a hard surface, an impact sequence triggers vibrations in various components or subsystems of the device. The time history of the excitation and thus the response of the component depends sensitively on the initial conditions of dropping and on the physical properties of the device and the underlying surface. In this paper, we explore how the response of a component is affected by its position in the device and by its physical parameters including mass distribution of the device and degree of energy absorption during impacts. An event-based numerical simulation of falling motion is used to determine the excitation of the component, which is modeled as a damped, linear oscillator. The maximal displacement of the oscillator is used as a measure of impact shock. Our results suggest that the appropriate design may decrease the mechanical shock by at least a factor of five. [ABSTRACT FROM AUTHOR]

This paper presents an algorithm for checking and enforcing passivity of behavioral reduced-order macromodels of linear time-invariant systems, whose frequency-domain (scattering) responses depend on external parameters. Such models, which are typically extracted from sampled input–output responses obtained from numerical solution of first-principle physical models, usually expressed as partial differential equations, prove extremely useful in design flows since they allow optimization, what-if or sensitivity analyses, and design centering. Starting from an implicit parameterization of both poles and residues of the model, as resulting from well-known model identification schemes based on the generalized Sanathanan–Koerner iteration, we construct a parameter-dependent skew-Hamiltonian/Hamiltonian matrix pencil. The iterative extraction of purely imaginary eigenvalues of the pencil, combined with an adaptive sampling scheme in the parameter space, is able to identify all regions in the frequency-parameter plane where local passivity violations occur. Then, a singular value perturbation scheme is set up to iteratively correct the model coefficients, until all local passivity violations are eliminated. The final result is a corrected model, which is uniformly passive throughout the parameter range. Several numerical examples demonstrate the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for the generation of reduced-order compact macromodels of analog circuit blocks (CBs) in highly integrated radio frequency and analog/mixed-signal design. The circuits under investigation are designed and assumed to operate at certain bias points, where they should perform as linear as possible. Therefore, they can be well approximated to first order by linearized transfer function models, assuming small-signal excitation around these operating points. This paper concentrates on a number of key aspects. First, a fully parameterized macromodeling flow is described, for the closed-form inclusion of external geometrical or design parameters in the macromodel responses. This aspect is important for fast optimization, design centering, and what-if analyses. Second, a parameterized DC correction strategy is presented, to guarantee that the DC response of the linearized macromodel matches to machine precision the true DC responses of the original CB. This aspect is fundamental when the macromodel is used in a system-level simulation deck that combines linearized and fully nonlinear models of other components. The main result of proposed approach is a SPICE-compatible reduced-order macromodel that can replace complex transistor-level CBs plus passive interconnect networks, thus enabling dramatic speedup in transient system-level analyses and signal integrity verifications. [ABSTRACT FROM AUTHOR]

Control of the capillary driven underfill flow process is a very important problem in flip chip technology in electronics packaging. The challenge here is to uniformly distribute fluids in the gap, which is composed of the chip and substrate and solder bumps. In this paper, we first present a conceptual model of the flow behavior of underfill materials, which has four stages, leading to the finding that the contact line jump phenomenon occurs at both entry and exit of the solder bumps. We then propose a more accurate model for describing the flow front based on the principles of mass conservation and force equilibrium. Another contribution of the present paper is the proposal of a computational model for describing the average capillary pressure difference with respect to the area of flow. The verification of these models is presented by comparing the result calculated with our model with the experimental result reported in the literature, which shows the superiority of the models proposed in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a model, based on timed automata (TA), of a real-time control system to measure the heights of solder balls of ball grid arrays (BGAs) on a printed circuit board and to determine whether the BGAs pass the height inspection routine. The TA model is actually a network of five TA, namely User, Controller, Motion, Camera, and Light, synchronized through user-defined channels. The dynamics of system components are simplified by a time delay which can be determined through experiments or roughly by experience. The simulation and verification in UPPAAL show that the model works fine without deadlock, and procedures after user operations demonstrate proper timely cooperation among the automata. The main design of hardware and software for the control system based on the model is also given in this paper, which has been successfully implemented in our laboratory. [ABSTRACT FROM PUBLISHER]

Conventional model-order reduction techniques used in circuit simulation guarantee the passivity and, consequently, the stability of the reduced circuit provided that the original circuit is passive. This excludes a large class of circuits that are stable but not necessarily passive. In this paper, an algorithm is described that guarantees the stability of the reduced circuit by construction. Numerical examples are presented that validate the efficiency and accuracy of the proposed method. [ABSTRACT FROM PUBLISHER]

An efficient and accurate table-based behavioral model extraction for high-speed input/output (I/O) buffer behavior is presented in this paper. The nonlinear current–voltage (I\--V) and charge–voltage (Q\--V) functions describing the gray-box model structure are extracted via least-squares methods using identification signals recorded from large signal transient simulation. The resulting continuous time-domain model is easily implemented as lookup table and leads to an increase in modeling accuracy, and a decrease in computation time, as is demonstrated in this paper. Finally, its application in a realistic signal integrity scenario is presented, demonstrating a superior performance compared to that of the I/O buffer information specification model. [ABSTRACT FROM PUBLISHER]

Power consumption and current fluctuation are continuously increasing in modern multicore systems. Such current flow may cause severe supply noise via off-chip and on-chip power delivery networks (PDN). Unexpected noise impacts the chip delay performance or even causes malfunction. In traditional practice, PDN designers assume a simple current source-based chip load, but it is often oversimplified, where the load current is modeled only for one or a few operation modes, and it is constant irrelevant to supply noise. In this paper, we propose a new chip load model that enables even off-chip PDN designers to assess the noise impact on circuit performance and use realistic current profile under supply voltage noise. We also integrate a control signal interface so that the model can switch the processor operation modes for finding unexpected noise behavior in design time and pursuing robust PDN design. Experimental results show that the proposed model mostly described by Verilog-A reproduces the current profile, current peak, and timing data well even while it achieves over $300\times $ run-time reduction compared to a transistor-level model. We also experimentally demonstrate that a land-side capacitor is helpful to improve processor timing performance in our test case. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

Industrial printed circuit boards (PCBs) are nonhomogeneous and anisotropic composites consisting of copper traces, glass-reinforced epoxy laminate (FR-4), solder mask, vias, and other features. Past efforts to model the elastic behavior of PCBs involve either simplistic assumptions or complicated and detailed modeling. In this paper, a practical method that gives reasonably accurate predictions of PCB’s elastic deformation is proposed. Three micromechanics models for fibrous composite, namely, the Cox–Krenchel, modified Cox lamina, and Pan, were employed in computing the mechanical properties of an industrial PCB. Copper trace orientations were accounted for in the modified Cox lamina model. A homogenization scheme based on the micromechanics models was implemented via the finite-element method to predict the board elastic bending and shear responses. Four-point bend and shear tests were conducted to verify all the three models. It was found that the models predict the bending stiffness well but overestimate its shear stiffness. In-plane strains, however, are in good agreement with the experiments. [ABSTRACT FROM AUTHOR]

Due to the upgrading of industrial technology and the maturity of electronic technology, product development technology, incorporating complex designs, has become highly sophisticated. Computer-aided engineering (CAE) has become a key procedure of high-tech industry. In this paper, CAE was used to simulate heat flow with CAE simulation software on the heat removal of a central processing unit (CPU) of a notebook computer component. A regression model was then obtained by using response surface methodology with the Box–Behnken design experimental matrix and by using different levels of experimental combinations. In addition, the optimal value of mean time between failures (MTBFs) was obtained by using the system response at unit cost as the response value. Finally, optimal settings were found to maximize the MTBF of a CPU. [ABSTRACT FROM AUTHOR]

One of the technical challenges of future naval surface combatants in utilizing medium-voltage dc distribution systems is common-mode coupling and galvanic isolation for managing faults and personal safety. The behavioral modeling reported in this paper is computationally efficient to be used in modeling distributed common-mode currents and potentials throughout the open-form conductor, which in this case is the ship structure. Physics-based modeling is used to form a multiport S-parameter behavioral model of the ship structure that complements the S-parameter models of parasitic paths to grounded equipment enclosures and cables sheaths. A time-domain common-mode conduction example is presented to illustrate the workflow that converts physics-based models of elementary hull elements into a complete S-parameter behavioral model of an arbitrary hull structure with power cables running along it. Because of the measurement and the simulation bandwidth limitation, the frequency domain model based on S-Parameters is band-limited. A novel approach for reconstructing the system impulse response in the time domain from its band-limited S-parameter model is introduced using continuous wavelet transform utilizing fast Fourier transform. [ABSTRACT FROM AUTHOR]

This paper presents a multi-resolution modeling approach using wavelet neural networks. A lithium battery model, which has three resolutions, is developed to depict the modeling approach. By combining the advantages of dyadic activation functions and the orthonormal property of wavelet functions, the developed battery model possesses two salient features. First, the model is built from a coarser approximation to a finer representation by adding more details incrementally. Second, the model at a low resolution is compatible with the model at a high resolution, which means that the parameters used in a low resolution can be directly incorporated into a high resolution without any modification. This paper's results show that this battery modeling provides great flexibility for users to choose a suitable resolution to meet their requirements for model accuracy and model execution speed. [ABSTRACT FROM PUBLISHER]

This paper presents a simulation method for the warpage that take places after the patterning process of printed circuit boards. To conduct an efficient as well as realistic simulation, a nonlinear thermo-elasticity problem with cure kinetics is approximated to a linear one by adjusting the thermal loading condition, which is the processing temperature where the stress-free state is assumed. This paper proposes a method that can determine such temperature based on a simple experiment. Moreover, methods for geometric modeling and meshing with finite elements are also proposed. With the use of the contact boundary conditions, complex copper patterns and dielectric layers are separately meshed and joined later. An experimental system is built for adjusting the thermal loading and verifying the simulation results. The numerical results are compared with experimental data to examine the validity of the method. [ABSTRACT FROM PUBLISHER]

A new thermal model based on a distributed and fast modeling approach for the modeling of gallium nitride (GaN) power devices is presented in this paper. The model is based on the application of Green’s function theory to obtain an analytical solution of the heat conduction equation. The model comprises an accurate, spatially distributed, and fast algorithm that calculates a 2-D thermal response at the 2-D electron gas level of GaN power devices in the steady-state and the transient regime. In comparison with finite element method finite-element model simulations, the model achieves a significant reduction of the computational time while retaining very good accuracy. The model shows strong capabilities for thermal analysis with respect to parameters that have a significant impact on the thermal behavior. Moreover, the nonlinear effect associated with the temperature-dependent thermal conductivity is encompassed together with the impact of package and ambience. As a validation study, the thermal behavior of packaged GaN devices is experimentally characterized by means of infrared thermography. An excellent agreement between the model results and experiments is observed. [ABSTRACT FROM AUTHOR]

Fitting of sampled frequency response data to a rational function is often required for macromodeling of advanced microelectronic packages. The pole residue equivalent system solver (PRESS) method was recently proposed, as a novel fitting method that builds the global fit from local fits, computed from at most three data points at an error peak. To increase the fitting accuracy of PRESS, the error-maxima agnostic PRESS (EMPRESS) was proposed, but it is computationally intensive as the central processing unit needs to sequentially perform the local fits at all the frequency sample points before choosing the best among them. In this paper, we propose the parallel optimized EMPRESS (POEMPRESS) to reduce the computational complexity of EMPRESS while improving the fitting performance. POEMPRESS optimizes both the EMPRESS algorithm and its implementation through: 1) simplified local fit types, enabling the algorithm to rely on at most two data points only, and 2) an algorithm that can be implemented on graphics processing units for rapid parallel computation and evaluation of local fits at all the frequency points. The proposed algorithm is demonstrated on the interconnects of a microelectronic package. The results show that POEMPRESS is effective in fast macromodeling of complex interconnects for signal and power integrity simulations. [ABSTRACT FROM AUTHOR]

As very large scale integration circuit speeds and density continue to increase, 3-D electromagnetic methods have become essential for the analysis, design, and verification of high-speed systems. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative to make them as compact as possible without compromising accuracy. To this aim, model-order reduction techniques can be successfully adopted. In this paper, we describe a partitioned Krylov subspace-based method for deriving reduced-order models directly from 3-D quasi-static partial element equivalent circuit models. The multiscale block decomposition method is adopted to speed-up the computation of the projection matrix; furthermore, the adaptive cross approximation and singular value decomposition techniques are used to achieve matrix compression exploiting the low-rank behavior of magnetic and electric field couplings. Results are presented on several examples to demonstrate the capabilities and speed of the proposed new method. [ABSTRACT FROM AUTHOR]

Design and analysis of high-speed SerDes channels primarily deal with ensuring signal integrity (SI) for desired electrical performance. SI is predominantly judged by time domain (TD) metrics: bit error rate (BER), eye-height (EH), and eye-width (EW). With increasing bit rates and stringent BER criteria, TD simulations are becoming compute-time-intensive. A full-factorial, cost-effective design space exploration for SI is made possible by learning-based mapping of frequency-domain S-parameter data to EH/EW. A major challenge in this mapping procedure is the identification of relevant S-parameter data, such as return loss, insertion loss, crosstalks, and the frequency points at which they are sampled. This paper outlines a methodology to identify the critical S-parameters at specific frequency points using information theory-based definition of data relevance using a fast correlation-based filter solution for feature selection. This technique is applied for identifying relevant features for generating artificial neural network-based prediction models of EH/EW within 2.5% accuracy for channels with high data rates and complex topologies. [ABSTRACT FROM PUBLISHER]

Fabrication process variations are a major source of yield degradation in the nanoscale design of integrated circuits (ICs), microelectromechanical systems (MEMSs), and photonic circuits. Stochastic spectral methods are a promising technique to quantify the uncertainties caused by process variations. Despite their superior efficiency over Monte Carlo for many design cases, stochastic spectral methods suffer from the curse of dimensionality, i.e., their computational cost grows very fast as the number of random parameters increases. In order to solve this challenging problem, this paper presents a high-dimensional uncertainty quantification algorithm from a big data perspective. Specifically, we show that the huge number of (e.g., 1.5 \times 10^27 ) simulation samples in standard stochastic collocation can be reduced to a very small one (e.g., 500) by exploiting some hidden structures of a high-dimensional data array. This idea is formulated as a tensor recovery problem with sparse and low-rank constraints, and it is solved with an alternating minimization approach. The numerical results show that our approach can efficiently simulate some IC, MEMS, and photonic problems with over 50 independent random parameters, whereas the traditional algorithm can only deal with a small number of random parameters. [ABSTRACT FROM PUBLISHER]

Ever-increasing complexity in high-speed electronic devices and systems presents significant computational challenges in the numerical analysis in terms of desired accuracy, efficiency, and scalable parallelism. The objective of this paper is to investigate high-resolution, high-performance full-wave field solvers for scalable electromagnetic simulations of product-level integrated circuits (ICs) and electronics. The emphasis is placed on advancing parallel algorithms that are provably scalable facilitating a design-through-analysis paradigm, and enabling concurrent multiscale modeling and computation. The capability and the benefits of the algorithms are validated and illustrated through complex 3-D IC and electronics applications. [ABSTRACT FROM PUBLISHER]

The feasibility of cointegration of new capacitors, named “through silicon capacitors” (TSCs) with “through silicon vias” in silicon interposers has recently been demonstrated. Two architectures of TSC are extensively investigated in this paper: “axial TSC” whose electrodes are connected on either sides of the silicon interposer and “radial TSC” with electrodes both connected to the metal layers of the back end of line. A general modeling method based on distributed cell segmentation is proposed for both architectures. Validation is performed by measurements from 1 kHz to 40 GHz (above the resonance frequency of the components). A comparative study between radial and axial architectures is performed, leading to the prediction of the performances of those new components. Finally, design rules are established for future integration for power delivery networks decoupling applications. [ABSTRACT FROM AUTHOR]

Thermal management of light-emitting diode (LED) chips is crucial for light extraction and lifetime. It is well known that the light output of an LED decreases with the elevated temperatures. For higher light extraction, the power input to the chip should be substantially high leading nonuniform current spreading and local joule heating at the chip active layers. However, this leads to a high amount of heat generation at the chip and a considerable amount of increase in the junction temperature. Besides shortening the lifetime of the chip, it also strongly affects the light output of the system. Although nominal driving currents for LEDs are around 350–400 mA, the ideal operating condition for the cost effectiveness at higher driving currents and corresponding efficiency of an LED chip is to be explored. In this paper, LED chips’ thermal and optical behaviors were investigated for different driving conditions while the board temperature is controlled using a thermoelectric cooler and the input current to the chip. The system was numerically investigated using a computational fluid dynamics software and validated with experimental studies. Consequently, a correlation for efficiency covering a wide range of operating conditions is presented. The efficiency of the LED that is obtained for 30 °C is 42%, whereas it drops to 30% for 50 °C board temperature. If one assumes a logarithmic relationship between the efficiency and the board temperature, the efficiency is expected to be around 20% for a typical LED operating temperature of between 80 °C and 100 °C. [ABSTRACT FROM AUTHOR]

In this paper, we present for the first time a rigorous crosstalk analysis of through silicon via (TSV) arrays consisting of several hundreds of TSVs in interposers with metallized surfaces, using the physics-based via (PBV) modeling approach for applications up to 500 GHz. The PBV modeling approach is valid for complete and almost complete metallizations of the substrate where radial wave propagation in the parallel-plate structure dominates the electromagnetic properties and is utilized with models of good accuracy for localized and propagating fields in the inhomogeneous dielectrics. The approach shows very good to good agreement of crosstalk results for frequencies up to 500 GHz in comparison to full-wave simulations and attains a speedup of at least two orders of magnitude in comparison to general-purpose simulators. The definition of a weighted power sum for total uncorrelated crosstalk is applied for all channels in the TSV array. These power sum results give more meaningful insights into the global effects of the parameter variations than single crosstalk contributions. Based on variations of several technology and design parameters of TSVs, we derive quantitative estimations of the impact of these parameters on the total crosstalk. [ABSTRACT FROM PUBLISHER]

This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulations. [ABSTRACT FROM PUBLISHER]

A new 3-D model for the die attach (DA) process is established and validated in this paper. With this model, the fluid flow characteristics of the DA process can be predicted accurately. Dynamic mesh and interface tracking method were adopted in the modeling to study the compression motion and the front of DA. A force driven model was conducted for the parametric studies of different bonding forces. The model for the DA process was validated by the four materials, AP1, CA1, CA4, and DM60 in the optimized condition. Bond line thickness can be predicted by the simulation with $\sim 20$ % accuracy. The simulation results show that the viscosity is one of the key properties, which has a significant effect on the required bonding force, bonding time, and DA contamination on the die top. Complete filling and DA contamination on the die top are two important standards to evaluate the good bonding force range in fluid dynamic analysis. Stress analysis illuminates that a fillet area is very critical and experiences highest stress during the reflow process. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a fast and accurate model of the vertical noise coupling from an on-chip switching-mode power supply (SMPS) to a low noise amplifier (LNA) in a stacked 3-D-IC. To achieve both speed and accuracy, the model is based on the analytic formulas of static R, L, and C parasitic extraction, and includes consideration of the phase difference in the on-chip inductors using a new iterative calculation method. The proposed model and the prediction of vertically coupled noise at the LNA output using the model are experimentally validated on a fabricated stacked 3-D-IC consisting of an on-chip SMPS and LNA. Good agreement with the measurements is confirmed in both the frequency domain and the time domain. The enhancements of the proposed model, including the broad model bandwidth (<4~GHz) as good as 3-D EM solver and 99% reduction of the simulation elapsed time (2 s) from 3-D EM solver, are confirmed. This paper also analyzes: 1) the impact of vertical noise coupling on the RF signal gain performance of the LNA and 2) the impact of variation in the stacking configuration, location, and thickness of the stacked LNA on the vertical noise coupling using the proposed model. Based on the results of our analysis, this paper proposes and verifies an effective method to reduce the vertical noise coupling using the proposed model. [ABSTRACT FROM PUBLISHER]

With the ever increasing heat loads dissipated by computer hardware, the ability to accurately characterize the cooling requirements in data centers is becoming crucial. Computational fluid dynamics modeling has proven in many cases to be adequate in providing a general understanding of the thermal environment in data centers. However, almost all analyses of data centers to this day are conducted in steady state. The effect of changes in hardware configurations and cooling resources on server rack inlet temperatures and airflow through servers has not been adequately investigated. This paper introduces transient modeling of data centers with changing power dissipations and computer room air-conditioning (CRAC) airflow rates. Transient modeling proves advantageous in monitoring temperature fluctuations due to airflow changes, which in some cases leads to insufficient cooling. In addition, modeling server thermal mass is shown to be important for transient analysis, as it can lead to overshoots in temperatures. Another segment of this paper looks at the effect of introducing thermal characteristics curves into CRAC modeling on server inlet temperature. All the cases presented show that fixed CRAC supply temperature is a non-valid assumption. [ABSTRACT FROM PUBLISHER]

This paper focuses on the derivation of an enhanced transmission-line model allowing the stochastic analysis of a realistic multiconductor interconnect. The proposed model, which is based on the expansion of the well-known telegraph equations in terms of orthogonal polynomials, includes the variability of geometrical or material properties of the interconnect due to uncertainties like fabrication process or temperature. A real application example involving the frequency-domain analysis of a coupled microstrip and the computation of the parameters variability effects on the transmission-line response concludes this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a novel methodology for high-level modeling of bus communication in embedded systems is introduced. It allows the dynamic evaluation of their signal integrity (SI) characteristics at the virtual prototyping step (i.e., before physical realization). The method is based on the association of functional and nonfunctional modules. Functional modules represent the ideal behavior of the system, while nonfunctional modules use neural networks to model SI effects. This approach was implemented in SystemC-AMS, using the timed data flow model of computation. The method is illustrated by a Universal Serial Bus (USB) 3.0 application, where modular and parameterizable models are introduced. The method achieved good accuracy (<5%) while allowing significant simulation speedup (up to 2000 times), compared with SPICE-based reference models. This methodology can be used to perform an early SI analysis in the virtual prototyping of bus communication in the embedded systems. [ABSTRACT FROM PUBLISHER]

Design space exploration and sensitivity analysis for electrical performance of high-speed serial links is a critical and challenging task for a robust, cost-efficient, and signal-integrity-compliant channel design. The generation of time-domain (TD) metrics like eye height and eye width at higher bit error rates requires longer bit sequences in TD circuit simulation, which is compute time intensive. Intelligent techniques to identify smaller design sets that cover the design space optimally may provide incorrect sensitivity analysis. This paper explores learning-based modeling techniques that rapidly map relevant frequency-domain metrics like differential insertion loss and total cross talk, in the presence of equalization, to TD metrics like eye height and eye width, thus facilitating a full-factorial design space sweep. Numerical results performed with multilayer-perceptron-based artificial neural network as well as least-squares support vector machine (LS-SVM) on Serial ATA 3.0 and Peripheral Component Interconnect Express Gen3 channels generate an average error of less than 2%. [ABSTRACT FROM PUBLISHER]

This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in glass interposers. By slicing TPVs horizontally into infinitesimally thin pieces and integrating along TPVs, an analytical solution was derived for the parasitic resistance ( $R$ ), while semianalytical expressions were derived for the parasitic inductance ( L$ ), capacitance ( C$ ), and conductance ( G magnitude and S_{21} phases being less than 0.01 dB and 1°, respectively. In addition, two dual-via chains of different lengths were designed, fabricated, and measured to benchmark the proposed model up to 20 GHz. The excellent consistency between them further proves the validity of the proposed model. Finally, the effect of the TPV taper was comprehensively studied on the RLCG parameters. It was found that the TPV taper was beneficial to reduce the parasitic capacitance and conductance by as much as 40%. Despite these benefits, tapered TPVs are not preferred, because the parasitic resistance and inductance are the dominant factors for TPVs in glass, and the TPV taper increases the parasitic resistance drastically and also increases the parasitic inductance by as much as 80%. [ABSTRACT FROM AUTHOR]

In this paper, we propose a chip-scale Chemical mechanical polishing (CMP) model based on the Greenwood–Williamson theory combining the effects of both the pad bulk deformation and the feature size, which are mainly responsible for global pressure distribution and feature-scale removal rate variation, respectively. A reference camber is first constructed to simulate the pad bulk deformation, which can be directly introduced into the global pressure distribution computation for incorporating the long-range characteristics of chip profiles. Then, both the effective curvature and the modified distribution function of pad asperity height are involved in the material removal rate. The model is first verified through some experimental data from CMP test structures and found to be in good agreement with the test data. For further validating the rationality and accuracy of the present model, some simulations are compared with our experimental data and discussed in detail. [ABSTRACT FROM PUBLISHER]

In this paper, an adjoint state-space dynamic neural network method for modeling nonlinear circuits and components is presented. This method is used for modeling the transient behavior of the nonlinear electronic and photonic components. The proposed technique is an extension of the existing state-space dynamic neural network (SSDNN) technique. The new method simultaneously adds the derivative information to the training patterns of nonlinear components, allowing the training to be done with less data without sacrificing model accuracy, and, consequently, makes training faster and more efficient. In addition, this method has been formulated such that it can be suitable for the parallel computation. The use of derivative information and parallelization makes training using the proposed technique much faster than the SSDNN. In addition, the models created using the proposed method are much faster to evaluate compared with the conventional models present in traditional circuit simulation tools. The validity of the proposed technique is demonstrated through the transient modeling of the physics-based CMOS driver, commercial NXP’s 74LVC04A inverting buffer, and nonlinear photonic components. [ABSTRACT FROM PUBLISHER]

This paper introduces a through-silicon-via (TSV) dispensing approach to accomplish the underfill process without a conventional reservoir. The vias function as entrances for dispensing or paths for fluid flow. Typically, the inflows of dispensing can be free droplets or a constant flow rate. The underfill flow in the gap includes two flowing stages: 1) the initial bidirectional flow and 2) the subsequent flow along chip edges. To find the factors affecting the filling time in TSV underfill, an analytical model is first built for the initial bidirectional underfill flow. The bidirectional flow is approximately modeled as a laminar and quasi-steady creeping flow between two parallel plates. The filling time in the initial stage is closely related to the flow radius, the inlet boundary, the material properties, the gap geometry, and the bump pattern. Afterward, the subsequent flow along the chip edges is investigated using a computational multiphase model. The governing equations of the computational model consist of mass conversation, momentum conversation, and element volume conservation. The computational results show that the chip length–width ratio also has a significant impact on the filling time if the inflow is free droplets. [ABSTRACT FROM AUTHOR]

In this paper, a full-wave transient domain decomposition method is proposed for solving multiscale electromagnetic problems. The proposed scheme is based on the unconditionally stable Laguerre finite-difference time-domain (Laguerre-FDTD) method. The entire computational domain is partitioned into several subdomains with independent meshing according to the physical sizes of each subdomain. Standard Laguerre-FDTD method is used to form the interior field equations of each subdomain, whereas interface field equations are formed by applying the equivalency between finite-element method and FDTD method. In addition, field continuity is enforced through the use of two sets of Lagrange multipliers at the domain interface. Schur complement is implemented for extracting the interface problem and each domain can be evaluated independently. Numerical results for multiscale structures are presented to demonstrate the capability, accuracy, and efficiency of the proposed method. [ABSTRACT FROM AUTHOR]

Mechanical contact caused using excessive probe force produces an oversized scrubbing mark that may result in damage to the die pad and the silicon chip breaking for thin wafer. Therefore, investigating the relationship between the wafer thickness and the limited breaking stress of the wafer, and applying this relationship as a basis for establishing suitable design rules for a multilayer needle layout are crucial. In this paper, two experimental techniques, three-point-bending test and ball-on-ring, were setup and carried out to measure the force-displacement relation of various wafer thicknesses (100–25 $\mu $ m). The results from the testing then coupled with finite-element analysis to reverse finding the breaking stress/strain as a function of wafer thickness. In addition, experimental setup with a single tungsten needle probe contact with Al pad were employed to investigate the relations between the overdrive, beam length, and scrub mark length. A 3-D computational probing simulation model was developed and verified against the experimental data. The model is then used to examine the effects of the beam length, overdrive distance (OD), and shooting angle on the maximum stress induced within the wafer. Finally, a four-layer probe card needle shape design has been demonstrated as a practical application example; it is shown that for a wafer thickness of 25 $\mu $ m and an OD of 60 $\mu $ m, the allowable shooting angles of a four-layer needle probe card are as follows: 1500 $\mu $ m and 0°–4° (Layer 1); 2100 $\mu $ m and 0°–9° (Layer 2); 3500 $\mu $ m and 0°–15° (Layer 3); and 4000 $\mu $ m and 0°–15° (Layer 4). [ABSTRACT FROM AUTHOR]

Underfill flow control is an important step in flip-chip technology and it can be generalized to fluid flow control in a porous medium, so solving this problem is of generalized implication to many other applications. The size of pores (i.e., clearance between the two solder bumps) in the flip-chip medium is less than 100 micrometers. In this paper, a new analytical model for permeability of the porous medium or solder bump flip-chip package is presented for two configurations of pores or solder of bumps (i.e., quadrilateral and equilateral triangular configurations). The model is shown to be more accurate than the existing model in the literature for the same purpose. Besides, the proposed model explicitly relates permeability with the structural parameters that describe the underfill space in flip-chip technology, namely, diameter of solder bumps, pitch of solder bumps, and gap height. In fact, there are two models, one for Newtonian fluids and the other for non-Newtonian fluids. These models allow us to optimize the structure of flip-chip packages in flip-chip technology or pores mediums in other applications. The models also provide a foundation for more precise control of the underfill flow process in flip-chip packages and the fluid filling process in pores mediums. [ABSTRACT FROM AUTHOR]

Heat sinks are widely used for cooling electronic devices and systems. Their thermal performance is usually determined by the material, shape, and size of the heat sink. With the assistance of computational fluid dynamics (CFD) and surrogate-based optimization, heat sinks can be designed and optimized to achieve a high level of performance. In this paper, the design and optimization of a plate-fin-type heat sink cooled by impingement jet is presented. The flow and thermal fields are simulated using the CFD simulation; the thermal resistance of the heat sink is then estimated. A Kriging surrogate model is developed to approximate the objective function (thermal resistance) as a function of design variables. Surrogate-based optimization is implemented by adaptively adding infill points based on an integrated strategy of the minimum value, the maximum mean square error approach, and the expected improvement approaches. The results show the influence of design variables on the thermal resistance and give the optimal heat sink with lowest thermal resistance for given jet impingement conditions. [ABSTRACT FROM PUBLISHER]

As the operating frequency of electronic devices increases and system miniaturization continues, designing power delivery networks (PDNs) that supply quality power throughout the system becomes very challenging. To guarantee successful performance of the PDN, an accurate and time-efficient simulation method that computes the PDN impedance is required. In this paper, we propose a computationally efficient PDN modeling method that analyzes multilayer power/ground planes. The proposed method solves the differential form of Maxwell's equation applied on the circuit representation of a plane pair. To use the analogy between the equations of the electromagnetic field and the equivalent circuit, a dual mesh is created on the metal surface. The use of a nonuniform triangular mesh enables effective discretization of multidimensional and irregular geometries. Moreover, the differential equation generates a sparse system matrix, which requires small computer resources. The proposed model is extended to multiple plane pairs, and the modeling of apertures located on any layer is also included. Simulation results show that the proposed method can solve complex structures with less computational effort than other modeling methods, while maintaining accuracy. In addition, the application of the absorbing boundary condition (ABC) to the proposed method is presented. Applying ABC to the plane boundaries prevents outgoing waves from reflecting back into the plane pair, hence removing plane resonances. The use of the first-order ABC results in a simple implementation and the results show good correlation with the results from a full-wave solver using higher order ABC. [ABSTRACT FROM AUTHOR]