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This article deals with the application of the partial least-squares (PLS) regression to the uncertainty quantification of an integrated wireless power transfer with 30 random variables. It considers the development of surrogate models using a limited set of training samples in order to estimate statistical quantities of the converter efficiency with a relatively low computational cost compared with the standard brute-force Monte Carlo (MC) simulation. The strength, the performance, and the features of the proposed modeling approach are then compared with the ones of an advanced probabilistic surrogate model combining the least-squares support vector machine (LS-SVM) and the Gaussian process regression (GPR). The MC simulation is considered as a reference. [ABSTRACT FROM AUTHOR]

This paper presents an alternative modeling strategy for the stochastic analysis of high-speed interconnects. The proposed approach takes advantage of the polynomial chaos framework and a fully SPICE-compatible formulation to avoid repeated circuit simulations, thereby alleviating the computational burden associated with traditional sampling-based methods such as Monte Carlo. Nonetheless, the technique offers very good accuracy and the opportunity to easily simulate complex interconnect topologies which include lossy and dispersive transmission lines, thus overcoming the limitations of previous formulations. Application examples involving the stochastic analysis of on-chip and on-board interconnects validate the methodology proposed. [ABSTRACT FROM AUTHOR]

In this paper, a stochastic modeling method is presented for the analysis of variability effects, induced by the manufacturing process, on interconnect structures terminated by general nonlinear loads. The technique is based on the solution of the pertinent stochastic Telegrapher's equations in time domain by means of the well-established stochastic Galerkin method, but now allows, for the first time in the literature, the inclusion of loads with arbitrary I-V characteristics at the terminals of the lines. The transient solution is obtained by combining the stochastic Galerkin method with a finite-difference time-domain scheme. The proposed technique is validated and illustrated with a meaningful application example, demonstrating its accuracy and efficiency. [ABSTRACT FROM AUTHOR]

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern system-in-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysis. [ABSTRACT FROM PUBLISHER]

This paper focuses on the derivation of an enhanced transmission-line model allowing the stochastic analysis of a realistic multiconductor interconnect. The proposed model, which is based on the expansion of the well-known telegraph equations in terms of orthogonal polynomials, includes the variability of geometrical or material properties of the interconnect due to uncertainties like fabrication process or temperature. A real application example involving the frequency-domain analysis of a coupled microstrip and the computation of the parameters variability effects on the transmission-line response concludes this paper. [ABSTRACT FROM PUBLISHER]

The modeling of the core power-delivery network of digital integrated circuits (ICs) is addressed by a black-box approach, leading to an n-port equivalent of the IC. The model parameters are estimated from external measurements carried out at the IC ports. The modeling procedure is demonstrated for a commercial NOR Flash Memory in 90 nm technology housed by a specifically-designed test fixture. [ABSTRACT FROM PUBLISHER]