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Thermal modeling of photonic integrated circuits (PICs) is required for circuit design and the development of thermal control algorithms. In this work, we present a methodology for obtaining a compact dynamic thermal $RC$ model of a PIC. PICs are sensitive to thermal coupling, and in this article, it is shown that traditional resistive coupling does not suffice, and a new coupling method is derived. The case study to which the new methodology is applied is a dense wavelength-division multiplexing ring filter with eight channels. With the obtained $RC$ model, the computational time is reduced from 5.5 h for finite element simulation to < 1 s for a single-step response. Using the compact model, circuit-level analysis of frequency response is carried out. Because of its high computational efficiency, the compact model opens possibilities for simulating thermal tuning algorithms. [ABSTRACT FROM AUTHOR]

In this article, we design, demonstrate, and characterize a 3-D printed package-level polymer jet impingement cooling solution on a $23\times23$ mm2 thermal test chip. The experimental hardware results for a nozzle pitch of 2 mm show that, with 1-kW power dissipation, at a coolant (deionized (DI) water) flow rate of 3 liters per minute (LPM), the measured average chip temperature increase is ~65 °C with a cooler pressure drop of 0.15 bar between the inlet and outlet connections. It is also shown that bare die cooling without lid [and thermal interface material (TIM)] shows better cooling performance than the lidded package. Second, an advanced 3-D printed manifold with an additional flow redistribution structure is demonstrated. The experimental results show that the improved design achieves a better chip temperature uniformity compared to the reference design, showing a reduction of the chip temperature gradient with a factor of 4 and 2.3 for a flow rate of 0.5 and 3 LPM, respectively, while no significant impact on the cooler pressure drop was measured. The numerical modeling studies predict an additional 15.4% thermal performance improvement, by reducing the nozzle pitch from 2 to 1 mm, for a flow rate of 3 LPM. [ABSTRACT FROM AUTHOR]

This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300- $\mu \text{m}$ nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve 15 × 104 W/m2 K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power. [ABSTRACT FROM AUTHOR]

The chip-level bare die direct liquid impingement jet cooling is regarded as a highly efficient cooling solution for high-performance applications. Furthermore, it shows potential to be integrated inside the chip package. In previous studies, we demonstrated this cooling concept using a prototype fabricated with mechanical micromachining using polymers. With the improvement of fabrication resolution, additive manufacturing or 3-D printing technology enables the fabrication of low-cost polymer microjet coolers with complex internal 3-D geometries and allows easy customization of the cooler design. In this paper, a chip-level impingement jet cooler with a $4 \times 4$ jet array and 575- $\mu \text{m}$ nozzle diameter is fabricated with high-resolution stereolithography, and assembled directly on the top of the bare die. The modeling study shows that the pressure drop in the 3-D printed cooler is reduced by 24% compared to the micromachined (MM) cooler with the same nozzle dimensions thanks to an improved more complex internal geometry. The fabrication quality and tolerances of the printed cooler are evaluated using optical measurements, scanning acoustic microscope (SAM) inspection, and cross-sectional analysis, showing a measured average nozzle diameter of 575 $\mu \text{m}$ compared to the designed nozzle diameter of 600 $\mu \text{m}$. Moreover, the 3-D computational fluid dynamics (CFD) simulations used in this paper are experimentally validated by chip temperature measurements. The achieved minimal thermal resistance of 3-D printed $4 \times 4$ cooler is 0.16 cm $^{2}\cdot \text{K}$ /W for a flow rate of 1000 mL/min. The benchmarking study shows the cooler size can be reduced by a factor of 6.5 by using the 3-D printing technology compared to the MM cooler. [ABSTRACT FROM AUTHOR]

In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented. The methodology is proven to be applicable to analyze the temperature evolution of real devices. A low-power package configuration with two different power dissipation scenarios, hotspot (HS) in the corner and HS in the center of the active region, has been considered for the validation. In this way, the importance of the package thermal impact on the definition of the final temperature profiles is highlighted. The error between the measurement and the FTM results remains always below 2.3 °C/W. Moreover, the model has been validated with respect to case studies concerning duty cycles of different durations. This proves the applicability of the model in defining the allowed duration of the chip activity before a maximum threshold temperature is reached. Finally, in this paper, the possibility to use a variable time-step approach in the transient FTM is presented together with the option of computing the temperature in individual points only. This is possible maintaining the same accuracy as if the fully resolved temperature maps would be calculated. [ABSTRACT FROM AUTHOR]

The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D integrated circuits (ICs). Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multiscale strategy, whose core is constituted by a highly resolved, convolution-based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time-dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite-element method results shows good accuracy. An error metric, to estimate a priori the need to include the package impact on top of the convolution-based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this paper. [ABSTRACT FROM AUTHOR]