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Simultaneous switching noise (SSN) is verified as a serious impact on the quality of power distribution and accuracy of the data acquisition system in the mixed signal circuits by modeling and simulating the single-stage output buffer at the driver side. To reduce SSN, a board-level slit-surface disturbance lattice electromagnetic bandgap structure is proposed. The corresponding 1-D equivalent transmission line model is established and lower and upper bound cutoff frequencies of the bandgap are derived. Suitable test boards are fabricated and measured to demonstrate the accuracy of the design concept. The measured SSN reduced to 65% and the signal jitter is decreased by 75% comparing with the solid power/ground plane, which proves that the isolation between the analog and the digital signals can be enhanced to improve the quality of power distribution, and provides a new method to improve precision for data acquisition and transmission in power monitoring system. The results show that the simulated, modeled, and measured results are consistent. [ABSTRACT FROM AUTHOR]

A 3-D model of multichip module (MCM) is built with ANSYS and the temperature field distribution is studied. A regression equation describing the relationship of structure parameters and material properties with the maximum chip junction temperature of MCM is made, which integrates the response surface methodology and ANSYS. Quantitative analysis of the effect of four design parameters on the maximum chip junction temperature of MCM is studied. The four design parameters are the thickness of the substrate, thermal conductivity of the substrate, thermal conductivity of the thermal grease, and convection heat transfer coefficient, respectively. The accuracy and validity of the regression equation are validated by simulation with ANSYS. In addition, the maximum error between the calculation value of the regression equation and the simulation value with ANSYS is 0.541^\circC. With the regression equation, the thermal optimization design results of the four parameters are Ktg=5~W/m~^{\circ}C, \delta=2.5~mm, Ks=290~W/m~^{\circ}C, and h=55~W/m^2~^\circC, which lead to the maximum chip junction temperature Tjmax=89.172^{\circ}C as the minimum value. [ABSTRACT FROM AUTHOR]