Search

This paper presents fuzzy ${c}$ -means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy ${c}$ -means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a ${k}$ -means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy. [ABSTRACT FROM AUTHOR]

Analog CMOS integrated circuits (ICs) designs depend typically on designer knowledge and experience, as such problems are multivariate and multiobjective, presenting many combinations of input variables to be investigated in order to meet the required specifications. Nowadays, the a posteriori approach is widely used to perform the optimization processes of analog CMOS ICs using evolutionary algorithms. However, these techniques are not totally able to explore potential solutions in specific regions of the Pareto front. Designers then have difficulty in choosing the best solution capable of achieving all desired specifications simultaneously among all the ones found. In this context, the a priori approach using fitness functions has become an important alternative method to overcome these issues of the a posteriori methodology. This paper aims to compare different fitness function profiles used in the a priori optimization processes to boost the effectiveness of the search processes in relation to robustness, accuracy, and yield in analog CMOS ICs designs. We show that the Gaussian profile, proposed here, applied to the lower limit, center value, and upper limit fitness functions is able to improve all the a priori optimization evolutionary techniques investigated, including the genetic, imperialist competitive, and shuffled frog leaping algorithms. [ABSTRACT FROM PUBLISHER]

High-cost specification tests of analog/RF devices have become a bottle-neck in reducing the overall cost of high-volume manufacturing (HVM) of systems on chip (SoCs) due to lengthy testing time and expensive test equipment. Especially for fabless semiconductor companies, test time reduction (TTR) is becoming an important priority for developing cost-effective design and manufacturing flow of SoCs. Toward this end, numerous approaches have been developed. In this paper, we point out an important practical issue in implementing feature-selection-based low-cost analog/RF test scheme: in HVM, similar specification tests are often bundled as test suites, which are tested as a whole function by automatic test equipment. Removing some tests in one test suite does not provide much saving on device testing time. We then propose a test-suite-based analog/RF TTR approach using canonical correlation, which aims at identifying correlations between two multivariate sets. We further enhance the incurred test escape by applying a data-driven defect-oriented approach. Experimental results in high-volume industrial data confirm the superiority of the proposed approach over existing methods in terms of both TTR and defective parts per million level. [ABSTRACT FROM PUBLISHER]

Domain-specific reconfigurable accelerators achieve high performance and energy efficiency by using specialized processing elements (PEs) instead of general-purpose alternatives. However, the process of designing, selecting, and refining the reconfigurable PEs that compose the accelerator fabric has remained a manual and difficult task. This paper presents reconfigurable accelerator design using iterative search for hardware (Radish) which is a full-stack framework for automatically identifying and generating PEs from an application corpus. Radish uses a genetic algorithm to iteratively search for and refine the proposed PEs with a compiler-in-the-loop to guide the search. We show that Radish-generated PEs can generalize to both larger instances of the same application as well as other previously unseen applications within the same domain. We evaluate a coarse-grain reconfigurable array (CGRA) architecture using our Radish-generated PEs and show it achieves a geometric mean improvement of up to $2.14\times$ and $2.4\times$ power and area, respectively, over an arithmetic logic unit-based CGRA designs. In terms of energy, our generated designs achieve a geometric mean improvement of $2.5\times$ but can achieve gains up to $28.9\times$. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGAs) are often used to accelerate multiple tasks simultaneously, working in a tightly coupled processor-coprocessor architecture. Recently, with the fast development of emerging memory technologies, multicontext FPGAs with high-density memories that support fast dynamic reconfiguration have become feasible. Compared with single-context FPGAs, multicontext FPGAs have a much higher on-chip configuration memory capacity but have not been thoroughly investigated to exploit their capabilities. In this paper, we investigate how to best utilize the capacity advantage of the multicontext FPGAs. We first propose a static placement strategy to place the requested hardware tasks with minimal area on the FPGA. We then optimize the running time of the static placement without sacrificing its solution quality. Along with the static placement, we propose collaborated online placement and scheduling strategies to manage the actual execution and reconfiguration of hardware tasks on a multicontext FPGA. Our experiments show that the static placement algorithm generates high quality placement solutions within a short time. Starting from the static placement solution, our collaborated online placer and scheduler schedules and places simultaneous acceleration tasks and reduces the acceleration task rejection rate significantly compared to a baseline design. [ABSTRACT FROM AUTHOR]

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts. [ABSTRACT FROM AUTHOR]

One of the main challenges in quantum computing is to ensure error-free operation of the basic quantum gates. There are various implementation technologies of quantum gates for which the distance between interacting qubits must be kept within a limit for reliable operation. This leads to the so-called requirement of neighborhood arrangements of the interacting qubits, often referred to as nearest neighbor (NN) constraint. This is typically achieved by inserting SWAP gates in the quantum circuits, where a SWAP gate between two qubits exchanges their states. Minimizing the number of SWAP gates to provide NN compliance is an important problem to solve. A number of approaches have been proposed in this regard, based on local and global ordering techniques. In this paper, a generalized approach for combined local and global ordering of qubits have been proposed that is based on an improved heuristic for cost estimation and is also scalable. The approach can be extended to N -dimensional arrangement of qubits, for any arbitrary values of N . Practical constraints, however, restrict the maximum value of N to 3. Extensive experiments on benchmark functions have been carried out to evaluate the performance in terms of SWAP gate requirements. 3-D organization of qubits shows average reductions of 6.7% and 37.4%, respectively, in the number of SWAP gates over 2-D and 1-D organizations. Also compared to the best 2-D and 1-D results reported in the literature, on the average 8.7% and 8.4% reductions, respectively, are observed. [ABSTRACT FROM PUBLISHER]

FlexRay is a hybrid communication protocol tailored to the requirements in the automotive domain, supporting both time-triggered and event-triggered communication with high data-rates. The time-triggered static segment is commonly used for in-vehicle communication while the event-triggered dynamic segment is used for diagnostics and configuration. This paper addresses the problem of synthesizing schedules for the static FlexRay segment for asynchronous scheduling, following the design approach of current automotive architectures. Previous approaches largely focused on FlexRay 2.1 while the few existing approaches for FlexRay 3.0 are nonoptimal in several aspects. As a remedy, our framework makes use of all new features of version 3.0 while supporting the still predominantly used FlexRay 2.1, making it backward compatible. The following approaches are proposed: 1) a single-stage integer linear programming (ILP) approach that determines an optimal solution but does not scale; 2) a multistage ILP for combining previously generated subsystem schedules to a global schedule. It clearly improves the scalability but is not optimal. The multistage approach allows to integrate and convert existing FlexRay 2.1 schedules into a FlexRay 3.0 schedule which is important for legacy reasons, i.e., to reduce testing and certification efforts; 3) a greedy heuristic which scales well and obtains high quality solutions in comparison with the optimal solution, but is unsuitable to integrate existing schedules; and 4) metaheuristic approaches based on genetic algorithms or simulated annealing to evaluate the benefits of the proposed approaches. [ABSTRACT FROM AUTHOR]

This paper presents OSCAR, an optimization methodology exploiting spatial correlation of multicore design spaces. This paper builds upon the observation that power consumption and performance metrics of spatially close design configurations (or points) are statistically correlated. We propose to exploit the correlation by using a response surface model (RSM), i.e., a closed-form expression suitable for predicting the quality of nonsimulated design points. This model is useful during the design space exploration (DSE) phase to quickly converge to the Pareto set of the multiobjective problem without executing lengthy simulations. To this end, we introduce a multiobjective optimization heuristic which iteratively updates and queries the RSM to identify the design points with the highest expected improvement. The RSM allows to consolidate the Pareto set by reducing the number of simulations required, thus speeding up the exploration process. We compare the proposed heuristic with state-of-the-art approaches [conventional, RSM-based, and structured design of experiments (DoEs)]. Experimental results show that OSCAR is a faster heuristic with respect to state-of-the-art techniques such as response-surface Pareto iterative refinement ReSPIR and nondominated-sorting genetic algorithm NSGA-II. In fact, OSCAR used a lower number of simulations to produce a similar solution, i.e., an average of 150 simulations instead of 320 simulations (NSGA-II) and 178 simulations (ReSPIR). When the number of design points is fixed to an average of 300, OSCAR achieves less than 0.6% in terms of average distance with respect to the reference solution while NSGA-II achieves 3.4%. Reported results also show that OSCAR can significantly improve structured DoE approaches by slightly increasing the number of experiments. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77\times better in power dissipation, 1.4\times better in area, and 1.58\times better in a composite metric of , and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the {\sim}{10\%} and {\sim}{11\%}$ improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively. [ABSTRACT FROM PUBLISHER]

Most signals between chips or packages in an electric circuit board require certain delays in order to achieve good timing. An extension of the circuit line that is proportional to the designated time delay has been a usual practice due to cost effectiveness. However, the layout of the line becomes dense due to the small size of packages or circuit boards, and this generates crosstalk, causing signal detection errors. In this paper, a design methodology of delay line layout for crosstalk minimization is developed using the genetic algorithm (GA). The GA requires a large number of function evaluations, and efficient calculation of crosstalk is proposed together with a new technique of generating random line, making offsprings, and mutation. Different optimum results have been obtained for different objectives and compared. Some of the designs were actually manufactured and experimentally tested, showing the validity of the optimum results. [ABSTRACT FROM AUTHOR]

This paper deals with a significant problem affecting embedded system design methods based on parameterized systems on a chip (SOCs). It proposes a strategy for exploration of the configuration space of a parameterized Soc architecture to determine an accurate approximation of the power/performance Pareto-front. The strategy is based on genetic algorithms and is thoroughly evaluated in terms of accuracy, efficiency, and scalability using SOC platforms that differ as regards both architectural model and complexity. The results obtained show that the proposed approach gives an excellent approximation of the Pareto-optimal front in very short exploration times (up to two orders of magnitude shorter than those required by one of the best known and widely referenced approaches in the literature). In addition, our approach possesses a good degree of scalability as performance levels are maintained even when the architectural complexity increases. [ABSTRACT FROM AUTHOR]

This paper proposes a variation of two-dimensional (2-D) cellular automata (CA) by adopting a simpler structure than the normal 2-D CA and a unique neighborship characteristic-asymmetric neighborshlp. The randomness of 2-D CA based on asymmetric neighborship is discussed and compared with one-dimensional (1-D) and 2-D CA. The results show that they are better than 1-D CA and could compete with conventional 2-D CA under certain array setting, output method, and transition nile. Furthermore, the structures of 2-D CA based on asymmetric neighborship were evolved using some multiobjective genetic algorithm. The evolved 2-D CA could pass DIEHARD tests with only 50 cells, which is less than the minimal number of cells (I.e., 55 cells) needed for neighborchanging 1-D CA to pass DIEHARD. In addition, a refinement procedure to reduce the cost of 2-D CA based on asymmetric neighborship is discussed. The minimal number of cells found is 48 cells for it to pass DIEHARD. The structure of this 48-cell 2-D CA is identical to that of the evolved 10 * 5 2-D CA, except that 2 horizontal cells in the evolved 10 * 5 2-D CA are removed. [ABSTRACT FROM AUTHOR]

Modern embedded systems are becoming increasingly multifunctional. The dynamism in multifunctional embedded systems manifests itself with more dynamic applications and the presence of multiple applications executing on a single embedded system. This dynamism in the application workload must be taken into account during the early system-level design space exploration (DSE) of multiprocessor system-on-a-chip (MPSoC)-based embedded systems. Scenario-based DSE utilizes the concept of application scenarios to search for optimal mappings of a multi-application workload onto an MPSoC. The scenario-based DSE uses a multi-objective genetic algorithm (GA) to identifying the mapping with the best average quality for all the application scenarios in the workload. In order to keep the exploration of the scenario-based DSE efficient, fitness prediction is used to obtain the quality of a mapping. This fitness prediction is performed using a representative subset of application scenarios that is obtained using co-exploration of the scenario subset space. In this paper, multiple fitness prediction techniques are presented: stochastic, deterministic, and a hybrid combination. Results show that, for our test cases, accurate fitness prediction is already provided for subsets containing only 1–4% of the application scenarios. Larger subsets will obtain a similar accuracy, but the DSE will require more time to identify promising mappings that meet the requirements of multifunctional embedded systems. [ABSTRACT FROM AUTHOR]

High-level synthesis (HLS) tools have been increasingly used within the hardware design community to bridge the gap between productivity and the need to design large and complex systems. When targeting heterogeneous systems, where the CPU and the field-programmable gate array (FPGA) fabric are both available to perform computations, a design space exploration (DSE) is usually carried out for deciding which parts of the initial code should be mapped to the FPGA fabric such as the overall system’s performance is enhanced by accelerating its computation via dedicated processors. As the targeted systems become more complex and larger, leading to a large DSE, the fast estimative of the possible acceleration that can be obtained by mapping certain functionality into the FPGA fabric is of paramount importance. Loop pipelining, which is responsible for the majority of HLS compilation time, is a key optimization toward achieving high-performance acceleration kernels. A new modulo scheduling algorithm is proposed, which reformulates the classical modulo scheduling problem and leads to a reduced number of integer linear problems solved, resulting in large computational savings. Moreover, the proposed approach has a controlled tradeoff between solution quality and computation time. Results show the scalability is improved efficiently from quadratic, for the state-of-the-art method, to linear, for the proposed approach, while the optimized loop suffers a 1% (geomean) increment in the total number of cycles. [ABSTRACT FROM AUTHOR]

This paper presents an efficient technique to perform design space exploration of a multiprocessor platform that minimizes the number of simulations needed to identify a Pareto curve with metrics like energy and delay. Instead of using semi-random search algorithms (like simulated annealing, tabu search, genetic algorithms, etc.), we use the domain knowledge derived from the platform architecture to set-up the exploration as a discrete-space Markov decision process. The system walks the design space changing its parameters, performing simulations only when probabilistic information becomes insufficient for a decision. A learning algorithm updates the probabilities of decision outcomes as simulations are performed. The proposed technique has been tested with two multimedia industrial applications, namely the ffmpeg transcoder and the parallel pigz compression algorithm. Results show that the exploration can be performed with 5% of the simulations necessary for the most used algorithms (Pareto simulated annealing, nondominated sorting genetic algorithm, etc.), increasing the exploration speed by more than one order of magnitude. [ABSTRACT FROM AUTHOR]

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements. [ABSTRACT FROM AUTHOR]

In this paper, we present COWLS, a hardware-software cosynthesis algorithm that targets embedded systems composed of servers and low-power clients that communicate with each other through a channel of limited bandwidth, e.g., a wireless link. A novel scheduling algorithm is used to pipeline the execution of tasks that serve multiple clients associated with a given server. COWLS simultaneously optimizes the price of the client-server system, the power consumption of the clients, and the response times of tasks that have only soft deadlines, while meeting all of the hard deadlines. It produces numerous solutions that trade off different architectural features, e.g., price, power consumption, and response time, of an embedded client-server system. As far as we know, this is the first synthesis algorithm of its kind. We present the experimental results for numerous pseudorandom examples, a low-power client-server camera system, as well as the rest of the benchmarks within a publicly released embedded system synthesis benchmark suite. [ABSTRACT FROM AUTHOR]

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not. [ABSTRACT FROM AUTHOR]

Nonlinear system design is often a multiobjective optimization problem involving the search for a design that satisfies a number of predefined constraints. The design space is typically very large since it includes all possible system architectures with different combinations of components composing each architecture. In this article, we address nonlinear system design space exploration through a two-step approach encapsulated in a framework called fast design space exploration of nonlinear systems (ASSENT). In the first step, we use a genetic algorithm to search for system architectures that allow discrete choices for component values or else only component values for a fixed architecture. This step yields a coarse design since the system may or may not meet the target specifications. In contrast to prior works on design space exploration that rely on forward design, we use an inverse design in step 2 to search over a continuous space and fine-tune the component values with the goal of improving the value of the objective function. We use a neural network (NN) to model the system response. The NN is converted into a mixed-integer linear program for active learning to sample component values efficiently. We illustrate the efficacy of ASSENT on problems ranging from nonlinear system design to the design of electrical circuits. Experimental results show that ASSENT achieves the same or better value of the objective function compared to various other optimization techniques for nonlinear system design by up to 53%. We improve sample efficiency by 6– $12\times $ compared to reinforcement learning-based synthesis of electrical circuits. [ABSTRACT FROM AUTHOR]

The design process of analog circuits is a challenging issue due to the nonidealities. Thus, analog IC design must be automated to shorten the design time and must be optimized to improve the important performance criteria, such as power dissipation, estimated chip occupation area, etc. In this work, a genetic algorithm (GA)-based approach is proposed for the low-pass filter design of IEEE 802.11n Wireless LAN. The performance criteria of OTA and CCII are modeled with an artificial neural network and transistor sizes of those blocks are determined with GA to improve the performance and to satisfy the constraints. The advantage of the proposed methodology is to eliminate infeasible solutions before starting circuit design by modeling the design constraints according to the transistor sizes allowed by production technology. The performance of the proposed method is tested with 0.18- $\mu \text{m}$ technology in CADENCE environment. [ABSTRACT FROM AUTHOR]

Provides information on a study which analyzed the application of stochastic combinatorial optimization techniques for the design automation of standard-cell placement. Details on statistical learning techniques such as simulated annealing and regression; Optimization and learning-based approach of cell-based layout; Methodology and discussion.

Presents information on a genetic algorithm for partitioning a hypergraph into disjoint graphs of minimum ratio cut. Background of genetic ratio-cut algorithm (GRCA); Experimental results; Conclusions.

We present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed. We present results on synthetic stacks created from ITC’99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. We also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem. [ABSTRACT FROM PUBLISHER]

We evaluate optimization techniques to reduce the necessary user interaction for inverse modeling applications as they are used in the technology computer-aided design field. Four optimization strategies are compared. Two well-known global optimization methods, simulated annealing and genetic optimization, a local gradient-based optimization strategy, and a combination of a local and a global method. We rate the applicability of each method in terms of the minimal achievable target value for a given number of simulation runs and in terms of the fastest convergence. A brief overview over the three used optimization algorithms is given. The optimization framework that is used to distribute the workload over a cluster of workstations is described. The actual comparison is achieved by means of an inverse modeling application that is performed for various settings of the optimization algorithms. All presented optimization algorithms are capable of evaluating several targets in parallel. The best optimization strategy that is found is used in the calibration of a model for silicon self-interstitial cluster formation and dissolution. [ABSTRACT FROM AUTHOR]

We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-μm CMOS technologies as well as a 0.13-μm floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-μm bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively. [ABSTRACT FROM AUTHOR]

An approach is presented for the high-level simulation and synthesis of discrete-time δΣ modulators based on a simulation-based optimization strategy. The high-level synthesis approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications—mainly accuracy (dynamic range) and signal bandwidth—are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator to realistically analyze and optimize the modulator performance. The approach has been implemented in a tool called Daisy (Delta-Sigma-Analysis and Synthesis). Experimental results are shown for both the analysis and synthesis capabilities, illustrating the effectiveness of the approach. The selected range of optimized ΔΣ modulator topologies as a function of the modulator specifications for a wide range of values indicate the capabilities of and the performance range covered by the tool. [ABSTRACT FROM AUTHOR]

Discusses a study that examined a developed floorplanner for radio-frequency circuits based on genetic algorithm (GA). Outline of the general floorplanning strategy; Layout of the radio-frequency limiting amplifier with slicing tree floorplan overlaid; Device-levl floorplanning; Results of the study.

Describes a genetic algorithm (GA) framework for sequential integrated circuit (IC) test generation. Various approach of genetic algorithm; Test generation in a GA framework; Selection and crossover scheme comparison for combinational circuits.

Describes a Genetic Algorithm for the Floorplan Area Optimization problem. Outline of genetic algorithms; Analysis of operator behavior; Mechanism for automatic optimization of activation probabilities.