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Effective transient power grid simulators are needed during design processes because a designed power grid needs to be numerously analyzed. This paper builds an efficient and reliable incremental power grid transient simulator, which we name it InTraSim, by integrating macro modeling techniques, sparse recovery mechanisms, an innovated pseudo-node value estimation method, and an initiated adaptive error control scheme. InTraSim is able to deal with not only element-value alterations of designs but also topology modifications of designs. [ABSTRACT FROM PUBLISHER]

Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9\times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model, the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment. [ABSTRACT FROM AUTHOR]

This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary ${N}$ -bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with voltage threshold adaptive memristor model. [ABSTRACT FROM AUTHOR]

Constructing algebraic polynomials using computer algebra techniques is believed to be state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach applies algebraic rewriting directly to the gate-level netlist, which has potential memory explosion problem. This paper introduces an algebraic rewriting technique based on the and-inverter graph (AIG) representation of gate-level designs. Using AIG-based cut-enumeration and truth table computation, an efficient order of algebraic rewriting is identified, resulting in dramatic simplifications of the polynomial under construction. An automatic approach, which further reduces the complexity of algebraic rewriting by handling redundant polynomials, is also proposed. [ABSTRACT FROM AUTHOR]

This paper proposes a technique, GALAXY, to speed up multicircuit simulation, where each circuit under simulation is identical in schematic but different in some parameters. GALAXY is based on the successive chord method, where the inverse Jacobian matrix ( J ^-1 ) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up single-circuit simulation by reusing J ^-1 between consecutive time steps. Compared with a traditional Newton–Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%. [ABSTRACT FROM PUBLISHER]

Resistive switching devices are nonlinear electrical components that have drawn great attention in the design of new technologies including memory devices and neuromorphic circuits. In this paper, an SPICE implementation of a novel compact model is presented and put under test by means of different circuit configurations. The model is based on two identical opposite-biased diodes in series with a resistor where the switching behavior is governed by the creation and rupture of multiple conductive channels. Results show that the model is stable under different input sources and amplitudes and, with special interest, in multielement circuits. The model is validated with experimental data available in the literature. Both the corresponding SPICE code and schematic are provided in order to facilitate the model use and assessment. [ABSTRACT FROM PUBLISHER]

This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions—called magnetic/electric hooks—on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed. [ABSTRACT FROM PUBLISHER]

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work. [ABSTRACT FROM AUTHOR]

Active cell balancing improves the performance of a battery pack by transferring charge from one cell to another. Associated design questions require multiple simulations with 100 cells over several hours. Since the most efficient transfer methods switch between phases in the kilohertz range, these simulations require high computational effort or reduced accuracy. To enable detailed analysis on a large scale, this paper includes state-of-the-art electrical battery models in active balancing simulation while keeping the computation effort for one transfer in the low millisecond range. This is achieved in three steps. First, we model the dynamics of each transfer phase using standard equivalent circuit abstraction. Next, we find closed form equations for the so-defined phase dynamics, yielding an iterative approach that saves computation time by replacing the numerical solver. Finally, we employ error control techniques to aggregate phases in that iteration, systematically reducing the millions of phase evaluations that would be necessary otherwise. Our experiments show that the speedup from equivalent circuit dynamics to error-controlled aggregation almost reaches five orders of magnitude while introducing virtually no additional error. This enables simulations of realistic balancing scenarios in less than a second and is hence suitable for design space exploration. [ABSTRACT FROM PUBLISHER]

Although molecular electronics is in its infancy, many significant advances have been reported in this field and, at present, it is necessary to study different types of materials that are potentially useful in molecular electronics and its properties. Experimental and theoretical studies have shown that almost all nanoscale devices such as molecular devices usually exhibit hysteresis characteristic due to various phenomena such as electron energy discreteness, electron tunneling, Coulomb blockade effects, etc. Some efforts have been made for modeling molecular electronics; however, not all of them support the hysteresis behavior. To the best of the authors’ knowledge, this paper for the first time proposes a general model for modeling the hysteresis behavior in molecular electronics. The proposed model is a HSPICE compatible circuit model and one of its main features is the ability to model both dc and ac behaviors of molecular electronic materials. The model can accept all amplitudes in the definite range, is continuous in the whole range and its parameters have minimum complexity resulting in maximum simplicity in terms of parameter extraction. Correct operation of the proposed circuit model and its accuracy are investigated by applying it to some hysteresis graphs reported in the literature, and the results are shown in this paper. [ABSTRACT FROM PUBLISHER]

With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design. [ABSTRACT FROM PUBLISHER]

Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and $1/f$ noise, which are important concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a long-standing open problem. It has been realized that the low-frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we present two fully nonstationary models for traps, a fine-grained Markov chain model and a coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we present subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We provide a detailed explication of these models with regard to their stochastic properties and develop carefully crafted circuit simulation techniques that are stochastically correct. We have implemented the proposed techniques in a MATLAB-based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low-frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator. [ABSTRACT FROM PUBLISHER]

Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model. [ABSTRACT FROM PUBLISHER]

Power grid (PG) simulation is critical for analysis and verification of power supply noises for robust and reliable integrated circuit (IC) designs. Computational demands to simulate PG for ICs with increasing complexity is never-ending. Cloud computing platforms can be leveraged to mitigate costs associated with making these resources available. However, since simulation data usually contains sensitive design information, simulating on third-party platforms lead to major security concerns. In this paper, we propose a framework for secure PG simulation on Cloud. A transformation algorithm to hide current excitations is presented, while still allowing a majority of computations to be completed on Cloud. We employ multiple compression strategies to significantly reduce communication overheads. Experiments show that our framework can achieve similar turn-around time as an insecure simulator on Cloud, while securing current excitations and output voltage vectors with reasonable communication and computational overheads. [ABSTRACT FROM PUBLISHER]

Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern very large scale integration circuits. However, as we approach sub-10 nm transistor technology, aggressive voltage, and gate length scaling will reduce the reliability of logic circuits due to the increasing impact of noise and variability effects. Therefore, designers need new tools to simulate logic circuits in the presence of noise. Time-domain analysis helps understand how transient faults affect a circuit and can guide designers in producing noise-resistant circuitry. However, standard approaches to modeling intrinsic noise sources in the time domain are computationally expensive. Moreover, small noise-driven fluctuations in electron occupation of circuit nodes introduce time-varying biasing point fluctuations, increasing the modeling complexity. To address these challenges, this paper introduces a new approach to modeling thermal noise and random telegraph signal noise directly in the time domain by developing and solving a series of stochastic differential equations. In comparisons to traditional SPICE-based simulations, our approach can provide three orders of magnitude speedup in simulation time without sacrificing accuracy. Moreover, we introduce a novel, iterative threshold-crossing algorithm, aimed at the efficient sampling of rare noise transients. We show that Monte-Carlo simulations based on this approach can detect rare high-amplitude single event transients that would be impossible to uncover with standard transient simulators. [ABSTRACT FROM PUBLISHER]

Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this scenario, this paper proposes the automatic conversion of analog models to C++-based languages, to remove the overhead of co-simulation with traditional virtual platform tools. The proposed methodology allows to convert a given analog description to either: 1) a fully equivalent description or 2) an abstract representation for faster simulation which models only the aspects of interest. Effectiveness and correctness have been proved on a number of case studies that highlight the effectiveness and potentiality of the proposed methodology. [ABSTRACT FROM AUTHOR]

Many critical electronic design automation (EDA) problems suffer from the curse of dimensionality, i.e., the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g., 3-D field solvers discretizations and multirate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g., full-chip routing/placement and circuit sizing), or extensive process variations (e.g., variability /reliability analysis and design for manufacturability). The computational challenges generated by such high-dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents “tensor computation” as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage. [ABSTRACT FROM PUBLISHER]

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost. [ABSTRACT FROM PUBLISHER]

Modeling and analysis of low-frequency noise, such as 1/ f and burst noise, with time-varying bias conditions is a long-standing open problem in circuit simulation. In this paper, we offer a solution for this problem and present a computational model for low-frequency noise. The merits of our model are twofold. First, it is fully nonstationary. It can represent noise processes with time-varying statistics that are tightly coupled to the circuit variables in a stochastically correct manner. Second, its mathematical structure allows the utilization of well-established, non-Monte Carlo noise analysis techniques which are orders of magnitude faster than their Monte Carlo counterparts. We first provide an overview of our noise model along with the legacy modeling techniques. We verify that, when used with fast non-Monte Carlo analysis methods, our noise model produces results with the same accuracy as computationally laborious Monte Carlo simulations. We then proceed to contrast our nonstationary noise model with the legacy modulated stationary model. As a typical instance, where the results produced by these two models differ significantly due to intricate nonstationary behavior, we analyze the switched biasing technique that was proposed in order to reduce low-frequency noise. As a case study, we examine the 1/ f noise behavior in the previously proposed coupled sawtooth oscillator circuit and show that, whereas simulations conducted with the legacy modulated stationary model suggest that no noise reduction is obtainable with switched biasing, our nonstationary noise model predicts the correct amount of noise reduction observed in previously published experimental data. [ABSTRACT FROM PUBLISHER]

Advances in sensing, computation, storage, and actuation technologies have entered cyber-physical systems (CPSs) into the smart era where complex control applications requiring high performance are supported. Neural networks (NNs) models are proposed as a predictive model to be used in model predictive control (MPC) applications. However, the ability to efficiently exploit resource hungry NNs in embedded resource-bound settings is a major challenge. In this paper, we propose priority neuron network (PNN), a resource-aware NNs model that can be reconfigured into smaller subnetworks at runtime. This approach enables a tradeoff between the model’s computation time and accuracy based on available resources. The PNN model is memory efficient since it stores only one set of parameters to account for various subnetwork sizes. We propose a training algorithm that applies regularization techniques to constrain the activation value of neurons and assigns a priority to each one. We consider the neuron’s ordinal number as our priority criteria in that the priority of the neuron is inversely proportional to its ordinal number in the layer. This imposes a relatively sorted order on the activation values. We conduct experiments to employ our PNN as the predictive model of a vehicle in MPC for path tracking. To corroborate the effectiveness of our proposed methodology, we compare it with two state-of-the-art methods for resource-aware NN design. Compared to state-of-the-art work, our approach can cut down the training time by 87% and reduce the memory storage by 75% while achieving similar accuracy. Moreover, we decrease the computation overhead for the model reduction process that searches for neurons below a threshold, from $ {O(n)}$ to $ {O}$ (log $ {n}$). [ABSTRACT FROM AUTHOR]

Automated analog circuit design is promising for increasing the design productivity and narrowing the time-to-market, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm quite smart in a way that the overall optimization process is self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experiments have demonstrated that the proposed smart-MSP is 2.6-12.5\times faster than the original MSP method, and is 1.3-2100\times faster than other state-of-the-art methods. [ABSTRACT FROM PUBLISHER]

Reuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects. [ABSTRACT FROM AUTHOR]

This paper describes an original simulation-based method to derive the stochastic properties of the output noise of switched-capacitor circuits which are used in sampled-data converters. The method relies on a linear time-varying approximation of the large-signal transient response of the switched circuits. It is shown how switched-capacitor-circuit noise and quantization noise, due to the presence of harsh comparators, can be analyzed in a unified frame where the data converter is modeled as a discrete-time system. [ABSTRACT FROM AUTHOR]

With the rising challenges in heat removal in integrated circuits (ICs), the development of thermal-aware computing architectures and run-time management systems has become indispensable to the continuation of IC design scaling. These thermal-aware design technologies of the future strongly depend on the availability of efficient and accurate means for thermal modeling and analysis. These thermal models must have not only the sufficient accuracy to capture the complex mechanisms that regulate thermal diffusion in ICs, but also a level of abstraction that allows for their fast execution for design space exploration. In this paper, we propose an innovative thermal modeling approach for full-chips that can handle the scalability problem of transient heat flow simulation in large 2-D/3-D multiprocessor ICs. This is achieved by parallelizing the computation-intensive task of transient temperature tracking using neural networks and exploiting the computational power of massively parallel graphics processing units. Our results show up to 35\times run-time speedup compared to state-of-the-art IC thermal simulation tools while keeping the error lower than 1^\circC. Speedups scale with the size of the 3-D multiprocessor ICs and our proposed method serves as a valuable design space exploration tool. [ABSTRACT FROM PUBLISHER]

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. This paper first introduces the properties of a desired thermal profile for better thermal matching of the matched devices. It then presents a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that the proposed approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works. [ABSTRACT FROM PUBLISHER]

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage. [ABSTRACT FROM PUBLISHER]

Dynamic thermal management (DTM) techniques are being widely used for attenuation of thermal hot spots in many-core systems. Conventionally, DTM techniques are analyzed using simulation and emulation methods, which are in-exhaustive due to their inherent limitations and cannot provide for a comprehensive comparison between DTM techniques owing to the wide range of corresponding design parameters. In order to handle the above discrepancies, we propose to use model checking, a state-space-based formal method, to model, evaluate, and compare DTM techniques across various functional and performance parameters. The suggested framework includes a modeling flow and a set of generic modules that realistically model many-core and DTM parameters like temperature, power, application, intercore communication and task migration, etc. For analysis purpose, the framework provides a common ground for comparing DTM techniques by formalizing DTM principles and performance parameters as a set of logical properties. These properties are verified for different task load configurations, e.g., multithreaded, malleable, and the applications which do not support migration. We analyze state-of-the-art central (c-) and distributed (d-) DTM techniques to demonstrate the generality and efficacy of our approach. Our formal analysis shows that the state-of-the-art cDTM technique performs better than dDTM in terms of achieving thermal stability, task migration, and communication overhead. We believe that conventional analysis methods do not facilitate such an exhaustive comparison among the DTM techniques. [ABSTRACT FROM AUTHOR]

Creating accurate data models describing the dynamics of physical phenomena in time and space is important in optimized control and decision making. Models highlight various trends and patterns. However, producing accurate models is challenging as different errors are introduced by sampling platforms with limited resources, e.g., insufficient sampling rates, data loss due to buffer overwriting, reduced communication bandwidth, and long communication delays. Furthermore, the dynamics of the environment, like mobile energy sources and sinks, might further increase errors as resources must be shared between the sampling and communication activities. This paper presents a procedure to systematically construct robust data models using samples acquired through a grid network of embedded sensing devices with limited resources, like bandwidth and buffer memory. Models are in the form of ordinary differential equations. The procedure constructs local data models by lumping state variables. Local models are then collected centrally to produce global models. The proposed modeling scheme uses a linear programming formulation to compute the lumping level at each node, and the parameters of the networked sensing platform, i.e., best data communication paths and bandwidths. Two algorithms are described to predict the trajectories of mobile energy sources/sinks as predictions can further reduce data loss and delays during communication. The computed parameters and trajectory predictions are used to configure the local decision making routines of the networked sampling nodes. Even though the procedure can be used to model a broader set of phenomena, experiments discuss the effectiveness of the method for thermal modeling of ULTRASPARC Niagara T1 architecture. Experiments show that the presented method reduces the overall error between 58.29% and 76.91% with an average of 68.87%, and communication delay between −11.49% and 57.62% with an average of 21.85%. [ABSTRACT FROM PUBLISHER]

This paper presents a procedure for the creation of versatile and powerful thermal compact models of integrated optical devices and demonstrates their use in an optical circuit level simulator. A detailed 3-D model of the device is first built using a meshless finite cloud method, producing a large linear sparse set of equations. This model is then reduced to a compact representation using a Krylov subspace model reduction (MR) technique. Such a reduced model is described by small dense matrices, but can reproduce the original temperature distribution within acceptable error. Three devices are used as demonstration models for the technique: a microdisc laser and two microring-based devices, a modulator, and an optical switch. All three devices are built in a silicon on oxide platform. Using MR the linear systems describing these models are reduced from thousands of unknowns to systems with less than 100 reduced variables. It is then demonstrated how the reduced compact models can be linked together to describe a complete optical system with solution errors of lower than 1%. Finally, it is shown how this reduced thermal model can be utilized in a circuit level opto-electronic circuit simulator and simulations are presented, demonstrating the effectiveness of the reduced models in speeding up simulation times or enabling otherwise intractable problems. [ABSTRACT FROM AUTHOR]

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools. [ABSTRACT FROM AUTHOR]

Fast and accurate thermal analysis is crucial for determining the propagation of heat and tracking the formation of hotspots in integrated circuits (ICs). Existing academic thermal analysis tools primarily use compact models to accelerate thermal simulations but are limited to linear problems on relatively simple circuit geometries. The Manchester Thermal Analyzer (MTA) is a comprehensive tool that allows for fast and highly accurate linear and nonlinear thermal simulations of complex physical structures including the IC, the package, and the heatsink. The MTA is targeted for 2.5/3-D IC designs but also handles standard planar ICs. The MTA discretizes the heat equation in space using the finite element method and performs the time integration with unconditionally stable implicit time stepping methods. To improve the computational efficiency without sacrificing accuracy, the MTA features adaptive spatiotemporal refinement. The large-scale linear systems that arise during the simulation are solved with fast preconditioned Krylov subspace methods. The MTA supports thermal analysis of realistic integrated systems and surpasses the computational capabilities and performance of existing academic thermal simulators. For example, the simulation of a processor in a package attached to a heat sink, modeled by a computational grid consisting of over 3 million nodes, takes less than 3 min. The MTA is fully parallel and publicly available. [ABSTRACT FROM AUTHOR]

We present a numerical modeling and simulation paradigm for multidomain, multiphysics systems with components modeled both in a lumped and distributed manner. The lumped components are modeled with a system of differential-algebraic equations (DAEs), whereas the possibly nonlinear distributed components that may belong to different physical domains are modeled using partial differential equations (PDEs) with associated boundary conditions. We address a comprehensive suite of problems for nonlinear coupled DAE–PDE systems including 1) transient simulation; 2) periodic steady-state (PSS) analysis formulated as a mixed boundary value problem that is solved with a hierarchical spectral collocation technique based on a joint Fourier–Chebyshev representation, for both forced and autonomous systems; 3) Floquet theory and analysis for coupled linear periodically time-varying DAE–PDE systems; 4) phase noise analysis for multidomain oscillators; and 5) efficient parameter sweeps for PSS and noise analyses based on first-order and pseudo-arclength continuation schemes. All of these techniques, implemented in a prototype simulator, are applied to a substantial case study: a multidomain feedback oscillator composed of distributed and lumped components in two physical domains, namely, a nano-mechanical beam resonator operating in the nonlinear regime, an electrical delay line, an electronic amplifier and a sensor-actuator for the transduction between the two physical domains. [ABSTRACT FROM AUTHOR]

We present deflection routing network on chip simulator (DNOC), a network-on-chip simulator. DNOC is primarily a deflection routing simulator, it simulates custom network topologies with detailed deflection router models, and a basic virtual channel router. DNOC can generate various statistics, such as network latency and power. We evaluate the simulator in three typical use cases. In stand-alone simulation, synthetic traffic generators are used to offer load to the network. In synchronous co-simulation, the simulator is integrated as a module within a larger system simulator with synchronization every simulated cycle. In the faster model-based co-simulation mode, a latency model is built, and retuned periodically at longer time intervals. We demonstrate co-simulation by running applications from the Rodinia and SPLASH-2 benchmark sets on mesh variants. DNOC is also able to run on multicore processors, speeding up the simulation of large networks. [ABSTRACT FROM AUTHOR]

Formal verification of a control system can be performed by checking if a model of its dynamical behavior conforms to temporal requirements. Unfortunately, adoption of formal verification in an industrial setting is a formidable challenge as design requirements are often vague, nonmodular, evolving, or sometimes simply unknown. We propose a framework to mine requirements from a closed-loop model of an industrial-scale control system, such as one specified in Simulink. The input to our algorithm is a requirement template expressed in parametric signal temporal logic: a logical formula in which concrete signal or time values are replaced with parameters. Given a set of simulation traces of the model, our method infers values for the template parameters to obtain the strongest candidate requirement satisfied by the traces. It then tries to falsify the candidate requirement using a falsification tool. If a counterexample is found, it is added to the existing set of traces and these steps are repeated; otherwise, it terminates with the synthesized requirement. Requirement mining has several usage scenarios: mined requirements can be used to formally validate future modifications of the model, they can be used to gain better understanding of legacy models or code, and can also help enhancing the process of bug finding through simulations. We demonstrate the scalability and utility of our technique on three complex case studies in the domain of automotive powertrain systems: a simple automatic transmission controller, an air-fuel controller with a mean-value model of the engine dynamics, and an industrial-size prototype airpath controller for a diesel engine. We include results on a bug found in the prototype controller by our method. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one. [ABSTRACT FROM AUTHOR]

The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more hierarchical structures to better exploit locality. To efficiently discover promising architectures within the rapidly growing search space, exhaustive exploration is replaced with tools that implement intelligent search strategies. Moreover, faster analytical models are preferred to costly simulations for estimating the performance and power of CMP architectures. The memory traffic generated by CMP cores has a cyclic dependency with the latency of the memory subsystem, which critically affects the overall system performance. Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks. The method can use customizable probabilistic models and solves the cyclic dependencies between traffic and latency by using a fixed-point strategy. By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces. The proposed techniques are shown to be very accurate and a promising strategy when compared to the results obtained by simulation. [ABSTRACT FROM PUBLISHER]

In this letter, a model-order-reduction method for generating piezoelectric compact models is presented. An Arnoldi-based technique is used to create compact models from the system matrices generated by a piezoelectric finite-element solver. The proposed approach also preserves the passivity of the generated compact models. The modeling results of a Rosen-type piezoelectric transformer are presented. The transient and frequency responses of the devices can be accurately simulated by the compact models. Moreover, compared with the full-meshed simulations, the compact models give computational speed-ups of at least two orders of magnitude. [ABSTRACT FROM PUBLISHER]

Many power management algorithms demand accurate and fine-grained runtime estimations of dynamic core power. In the absence of fine-grained power sensors, model-based estimations are needed. Such power models commonly approximate the switching activity of logic gates using performance counters while assuming a linear performance counter/power relation at a fixed frequency and voltage. It has been shown that this relation cannot be captured accurately enough with purely linear models and that well-established nonlinear modeling techniques, e.g., polynomial modeling, easily overfit the underlying performance/power relations. Although neural-network-based modeling has shown to accurately capture nonlinear relations, it has a large training and inference overhead which is too high for fine-grained models on core-level and estimation rates in the range of 1–10 kHz. We propose a methodology for nonlinear transformation of specific performance counters to increase power modeling accuracy at constant frequency and voltage with a relatively low overhead for both model generation and run-time application over a linear model. Furthermore, we use least-angle regression (LARS) to determine a ranking of the performance counter inputs for use in linear and nonlinear modeling and show that the transformed performance counters are better suited for power modeling. The generated dynamic power model consisting of a nonlinear transformation block and a linear regression block reduces relative estimation error on average by 4% and in worst-case scenarios by 7% compared to state-of-the-art fine-grained linear power models. Compared to a state-of-the-art polynomial regression model our proposed approach reduces the relative estimation error by 10% in worst-case scenarios. [ABSTRACT FROM AUTHOR]

This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation. [ABSTRACT FROM AUTHOR]

A black-box method for modeling the time-domain response of integrated circuits (ICs) based on echo state networks is proposed. The number and value of the input and feedback delays required for modeling nonlinear systems with memory are detected automatically, and the training procedure is very fast and robust. The resulting models can be implemented in any hardware description language. The proposed modeling approach is applied to three test cases that cover a wide range of analog behavior. The achieved accuracy is comparable to the reference modeling method, and, depending on the complexity of the modeled IC, the simulation speed-up factor is in the order between 10 and 100. [ABSTRACT FROM AUTHOR]

Recently, new technologies have emerged in industrial automation platforms. A rapid modeling and simulation environment is required to integrate these new technologies with existing devices and platforms to reduce the design effort and time to market. System-level modeling is a popular design technique that provides early simulation, verification, and architectural exploration. However, integration of real devices with system models is quite challenging due to synchronization and hard real-time constraints in industrial automation. SystemC is the most commonly used system-level language in hardware–software codesign. However, SystemC lacks interfaces for the integration of system (virtual) models with real (physical) devices. We introduce the hybrid channel concept to clearly define the integration interface. Hybrid channel incorporates both real-to-virtual and virtual-to-real communication functions by solving synchronization issues while satisfying the real-time constraints. We successfully demonstrated the usability of our framework in industrial systems that utilize BACNet and Ethernet. We also developed a mathematical model that correctly estimates the results of our experiments. To the best of our knowledge, this is the first framework and mathematical model for SystemC in industrial automation domain. [ABSTRACT FROM AUTHOR]

In this letter, we report an approach combining piecewise-linear (PWL) approximation with general orthogonal polynomials to efficiently simulate large nonlinear descriptor systems in time-domain. The main idea of this approach is first to approximate a nonlinear function by a piecewise-linear representation. Then, using the recursive formulae of general orthogonal polynomials, orthonormal bases can be produced for fast simulation of the PWL model. The effectiveness of our approach is demonstrated on two nonlinear circuit models. [ABSTRACT FROM PUBLISHER]

Spatial processing of sparse, irregular, double-precision floating-point computation using a single field-programmable gate array (FPGA) enables up to an order of magnitude speedup (mean 2.8\times speedup) over a conventional microprocessor for the SPICE circuit simulator. We develop a parallel, FPGA-based, heterogeneous architecture customized for accelerating the SPICE simulator to deliver this speedup. To properly parallelize the complete simulator, we decompose SPICE into its three constituent phases—model evaluation, sparse matrix-solve, and iteration control—and customize a spatial architecture for each phase independently. Our heterogeneous FPGA organization mixes very large instruction word, dataflow and streaming architectures into a cohesive, unified design to match the parallel patterns exposed by our programming framework. This FPGA architecture is able to outperform conventional processors due to a combination of factors, including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and streaming, overlapped processing of the control algorithms. We demonstrate that we can independently accelerate model evaluation by a mean factor of 6.5\times (1.4\--23\times) across a range of nonlinear device models and matrix solve by 2.4\times(0.6\--13\times) across various benchmark matrices while delivering a mean combined speedup of 2.8\times(0.2\--11\times) for the composite design when comparing a Xilinx Virtex-6 LX760 (40 nm) with an Intel Core i7 965 (45 nm). We also estimate mean energy savings of 8.9\times (up to 40.9\times) when comparing a Xilinx Virtex-6 LX760 with an Intel Core i7 965. [ABSTRACT FROM PUBLISHER]

We present a projection-based nonlinear model order reduction method, named model order reduction via quadratic-linear systems (QLMOR). QLMOR employs two novel ideas: 1) we show that nonlinear ordinary differential equations, and more generally differential-algebraic equations (DAEs) with many commonly encountered nonlinear kernels can be re-written equivalently in a special representation, quadratic-linear differential algebraic equations (QLDAEs), and 2) we perform a Volterra analysis to derive the Volterra kernels, and we adapt the moment-matching reduction technique of nonlinear model order reduction method (NORM) refid="ref1" to reduce these QLDAEs into QLDAEs of much smaller size. Because of the generality of the QLDAE representation, QLMOR has significantly broader applicability than Taylor-expansion-based methods refid="ref1" refid="ref2"refid="ref3" since there is no approximation involved in the transformation from original DAEs to QLDAEs. Because the reduced model has only quadratic nonlinearities, its computational complexity is less than that of similar prior methods. In addition, QLMOR, unlike NORM, totally avoids explicit moment calculations, hence it has improved numerical stability properties as well. We compare QLMOR against prior methods refid="ref1"refid="ref2" refid="ref3" on a circuit and a biochemical reaction-like system, and demonstrate that QLMOR-reduced models retain accuracy over a significantly wider range of excitation than Taylor-expansion-based methods refid="ref1"refid="ref2" refid="ref3". QLMOR, therefore, demonstrates that Volterra-kernel-based nonlinear MOR techniques can in fact have far broader applicability than previously suspected, possibly being competitive with trajectory-based methods (e.g., trajectory piece-wise linear reduced order modeling refid="ref4") and nonlinear-projection-based methods (e.g., maniMOR refid="ref5"). [ABSTRACT FROM PUBLISHER]