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Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling, and floorplanning on partially dynamically reconfigurable FPGAs. The partition, schedule, and floorplan of the tasks are represented by the partitioned sequence triple (P-ST) (PS, QS, RS), where (PS, QS) is a hybrid nested sequence pair for representing the spatial and temporal partitions, as well as the floorplan, and RS is the partitioned dynamic configuration order of the tasks. The floorplanning and scheduling of task modules can be computed from the P-ST in ${O}$ (${n}^{{2}}$) time. To integrate the exploration of the scheduling and floorplanning design space, we use a simulated annealing-based search engine and elaborate a perturbation method, where a randomly chosen task module is removed from the partition sequence triple and then reinserted into a proper position selected from all the ${O}$ (${n}^{ {3}}$) possible combinations of partition, schedule and floorplan. We also prove a sufficient and necessary condition for the feasibility of the partitioning of tasks and scheduling of task configurations, and derive conditions for the feasibility of the insertion points in a P-ST. The experimental results demonstrate the efficiency and effectiveness of the proposed framework. [ABSTRACT FROM AUTHOR]

In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a critical technique to provide vertical connections. However, the yield and reliability challenge of TSV in industry is one of key obstacles to adopt the 3-D ICs technology. Various fault-tolerance structures by using additional spare TSVs (s-TSVs) to repair faulty functional TSVs (f-TSVs) have been proposed in literature for yield and reliability enhancement. However, these structures are formed in standard cell placement stage where all the f-TSVs are already placed. In reality, since the s-TSVs can be only inserted into the whitespace, the quality of the generated repair solution is strongly dependent on the whitespace distribution. In this paper, we propose an efficient TSV planning and repair framework in floorplanning stage, which takes nonuniform TSV distribution and clustered TSV defect-distribution into account. The proposed framework mainly consists of four stages: 1) a whitespace redistribution algorithm that uses a probability-based strategy to make the whitespace distribution more reasonable for the f-TSV planning. Subsequently, a convex-cost flow-based model for f-TSV allocation considering the fault clustering; 2) a top-down globally partitioning combined with a bottom-up locally merging to partition f-TSVs into groups with minimum hardware cost; 3) the min-cost max-flow algorithm for s-TSV allocation with minimum wirelength overhead; and 4) an integer linear programming-based model to form a fault-tolerance structure with minimum multiplexer delay overhead. The experimental results demonstrate that the proposed repair framework can improve the yield with minimum hardware cost and multiplexer delay overhead. [ABSTRACT FROM AUTHOR]