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Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular spin-transfer torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a logically adaptable retention time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications’ runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications’ needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications’ requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads. [ABSTRACT FROM AUTHOR]

Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integrate platform-level characteristics into the control algorithms design are largely missing. With the emergence of cyber-physical systems (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms, leading to work on networked control systems and computation-aware control algorithms design. However, there has so far been no work on integrating the characteristics of a memory architecture into the design of control algorithms. In this paper we, for the first time, show that accounting for the impact of on-chip memory (or cache) reuse on the performance of control applications motivates new techniques for control algorithms design. This leads to significant improvement in quality of control for given resource availability, or more efficient implementations of embedded control applications. We believe that this paper opens up a variety of possibilities for memory-related optimizations of embedded control systems, that will be pursued by researchers working on computer-aided design for CPS. [ABSTRACT FROM PUBLISHER]

Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems. Dynamic reconfiguration techniques are widely studied for improving cache energy without considering the implications of cache vulnerability. Maintaining a useful data longer in the cache can be beneficial for energy improvement due to reduction in miss rates, however, longer data retention negatively impacts the vulnerability due to soft errors. This paper studies the tradeoff between energy efficiency improvement and reduction in cache vulnerability during cache reconfiguration. We propose a heuristic approach for both intertask and intratask cache reconfiguration in multitasking systems. Experimental results demonstrate that our proposed approach can significantly improve both vulnerability (25% on average) and energy efficiency (21% on average) for data cache without violating real-time constraints. [ABSTRACT FROM AUTHOR]

Modern embedded systems, such as automotive, are physically distributed with an increasing number of microcontrollers and buses. They support complex functions such as active safety and autonomous driving features with a high degree of data dependencies. The most common configuration uses periodic activation of tasks and messages coupled with priority-based scheduling. Selecting task and message parameters so that end-to-end deadlines are met can be very challenging, since such deadlines are enforced across a set of microcontrollers and buses. In this paper, we address the problem of optimal selection of task and message activation periods and priorities. Existing approaches cannot scale to large designs and have to settle to optimize period or priority separately, largely due to the complexity of response time analysis techniques. Instead, we present a new, unified framework that simultaneously optimizes period and priority assignment. It avoids the pitfalls of existing approaches by abstracting the response time calculation with the new concept of maximal unschedulable period and deadline assignment. We demonstrate with two industrial case studies that our approach runs magnitudes faster than existing approach on period optimization, while providing substantially better solutions. [ABSTRACT FROM AUTHOR]

The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the performance of an application. Modern embedded processors often feature cache locking mechanisms that allow memory blocks to be locked in the cache under software control. Cache locking was primarily designed to offer timing predictability for hard real-time applications. Hence, prior techniques focus on employing cache locking to improve the worst-case execution time. However, cache locking can be quite effective in improving the average-case execution time of general embedded applications as well. In this paper, we explore static instruction cache locking to improve the average-case program performance. We introduce temporal reuse profile (TRP) to accurately and efficiently model the cost and benefit of locking memory blocks in the cache. We consider two locking mechanisms, line locking and way locking. For each locking mechanism, we propose a branch-and-bound algorithm and a heuristic approach that use the TRP to determine the most beneficial memory blocks to be locked in the cache. Experimental results show that the heuristic approach achieves close to the results of branch-and-bound algorithm and can improve the performance by 12% on average for 4 KB cache across a suite of real-world benchmarks. Moreover, our heuristic provides significant improvement compared to the state-of-the-art locking algorithm both in terms of performance and efficiency. [ABSTRACT FROM PUBLISHER]

Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this paper, we propose a methodology to minimize the energy consumption of NoC without violating the prespecified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline—the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets. Furthermore, we design a feedback-control strategy to enable dynamic frequency and voltage scaling on the network routers in conjunction with the energy optimization algorithm. It can flexibly improve the energy-efficiency of the overall network in response to sporadic traffic patterns at runtime. [ABSTRACT FROM AUTHOR]

Energy consumption and the associated environmental impact are a pressing challenge faced by the transportation sector. Emerging electric-drive vehicles have shown promises for substantial reductions in petroleum use and vehicle emissions. Their success, however, has been hindered by the limitations of energy storage technologies. Existing in-vehicle lithium-ion battery systems are bulky, expensive, and unreliable. Energy storage system (ESS) design and optimization is essential for emerging transportation electrification. This paper presents an integrated ESS modeling, design, and optimization framework targeting emerging electric-drive vehicles. A large-scale ESS modeling solution is first presented, which considers major runtime and long-term battery effects, and uses fast frequency-domain analysis techniques for efficient and accurate characterization of large-scale ESS. The proposed design framework unifies design-time optimization and runtime control. This conducts statistical optimization for ESS cost and lifetime, which jointly considers the variances of ESS due to manufacture tolerance and heterogeneous driver-specific runtime usage. This optimizes ESS design by incorporating complementary energy storage technologies, e.g., lithium-ion batteries and ultracapacitors. Using physical measurements of battery manufacture variation and real-world user driving profiles, our experimental study has demonstrated that the proposed framework effectively explores the statistical design space and produces cost-efficient ESS solutions with statistical system lifetime guarantees. [ABSTRACT FROM AUTHOR]

In this paper, we propose a user-centric design methodology targeting heterogeneous embedded systems-on-chip where communication happens via the network-on-chip approach. More precisely, in this new design methodology, we consider explicitly the information about the user experience and apply machine learning techniques to develop a design flow which aims at minimizing the workload variance; this allows the system to better adapt to different types of user needs and workload variations. Our experimental results show that by considering the user experience into the design space exploration step, the system platforms generated by our approach achieve more than 30% energy savings, on average, compared to the single platform derived from the traditional design flow; this implies that each system configuration we generate is highly suitable for the targeted class of user and workload behaviors. [ABSTRACT FROM AUTHOR]