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A methodology to create and develop electrical compact models for memristive devices is presented. It comprises a six-step algorithm that uses experimental data of memristive devices in order to obtain a compact model suitable for circuit-level simulations. The model methodology makes use of the definition of the intrinsic variables of memristive systems, to obtain the state map that describes the system, from which the mathematical expressions of the model are obtained. In order to illustrate the usage of the algorithm, a compact memristive model is developed by using experimental data from a TiO2-based resistive switching (RS) device. The resulting mathematical model is compared to the experimental data by computing the mean absolute percentage error (MAPE) between both, which results in 11%, and reduces to 6% after a piecewise approach. The circuit-level representation is implemented using a SPICE macromodel and a Verilog-A module, from which the memristive behavior is also properly reproduced. [ABSTRACT FROM AUTHOR]

The general diode equation or the nonideal diode equation is the foundation of circuit models of active devices for the past several decades. Apart from the effect of a p-n junction, this equation also accounts for the series bulk resistance of a diode. Despite a reasonable agreement of the equation with measured IV characteristics, it is shown here that the equation is incompatible with basic theories of circuits and systems. Therefore, a modification in the equation is proposed to remove this incompatibility. This modified equation leads to a compact model of a p-n junction diode that has an excellent agreement with the measured IV characteristics. [ABSTRACT FROM AUTHOR]

This article explores the weight binarization of the deconvolution-based generator in a generative adversarial network (GAN) for memory saving and speedup of image construction on the edge. This article suggests that different from convolutional neural networks (including the discriminator) where all layers can be binarized, only some of the layers in the generator can be binarized without significant performance loss. Supported by theoretical analysis and verified by experiments, a direct metric based on the dimension of deconvolution operations is established, which can be used to quickly decide which layers in a generator can be binarized. Our results also indicate that both the generator and the discriminator should be binarized simultaneously for balanced competition and better performance during training. The experimental results on CelebA dataset with DCGAN and original loss functions suggest that directly applying state-of-the-art binarization techniques to all the layers of the generator will lead to $2.83\times $ performance loss measured by sliced Wasserstein distance compared with the original generator, while applying them to selected layers only can yield up to $25.81\times $ saving in memory consumption, and $1.96\times $ and $1.32\times $ speedup in inference and training, respectively, with little performance loss. Similar conclusions can also be drawn on other loss functions for different GANs. [ABSTRACT FROM AUTHOR]

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

A technique for extracting statistical compact model parameters using artificial neural networks (ANNs) is proposed. ANNs can model a much higher degree of nonlinearity compared to existing quadratic polynomial models and, hence, can even be used in sub-100-nm technologies to model leakage current that exponentially depends on process parameters. Existing techniques cannot be extended to handle such exponential functions. Additionally, ANNs can handle multiple input multiple output relations very effectively. The concept applied to CMOS devices improves the efficiency and accuracy of model extraction. Results from the ANN match the ones obtained from SPICE simulators within 1%. [ABSTRACT FROM AUTHOR]

In this letter, a model-order-reduction method for generating piezoelectric compact models is presented. An Arnoldi-based technique is used to create compact models from the system matrices generated by a piezoelectric finite-element solver. The proposed approach also preserves the passivity of the generated compact models. The modeling results of a Rosen-type piezoelectric transformer are presented. The transient and frequency responses of the devices can be accurately simulated by the compact models. Moreover, compared with the full-meshed simulations, the compact models give computational speed-ups of at least two orders of magnitude. [ABSTRACT FROM PUBLISHER]

In this paper, we present a methodology of generating nonlinear microfluidic macromodels for system-level simulations of 3-D microchannels using the Galerkin-based technique. Each generated macromodel consists of a low-order model and a few basis functions. For generating the basis functions, the ensembles of snapshots of fluidic field distributions are calculated by a finite-element-method or finite-volume-method solver, and then, the proper orthogonal decomposition is employed to extract the basis functions from the ensembles. For creating the low-order model, the Galerkin condition is used to formulate a set of simple ordinary differential equations. Compared with the full-meshed simulations, the generated macromodels not only provide accurate results (i.e., about 1% error) but also give computational speedups of at least three orders of magnitude. Also, the scaling and reusability of the generated macromodels are described and discussed. Furthermore, the macromodels of complicated channels can also be created by assembling the macromodels of other simple channels. The errors between the results by the assembled macromodels and the results by the full-meshed models are less than 2%. [ABSTRACT FROM AUTHOR]

A compact, efficient electrical dual-circuit topology for the representation of transient thermal coupling is presented. Based on controlled sources, the method allows an arbitrary level of complexity to be used for each self and coupled response. Two possible variations on the circuit form, and the resulting requirements for model extraction, are developed. The method is applied to the modeling of transient thermal self-heating and coupling data for a pair of thermal sources representative of integrated device structures in semi-infinite homogeneous as well as trench-isolated substrates. [ABSTRACT FROM AUTHOR]