1. Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs
- Author
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Bethur, Nesara Eranna, Agnesina, Anthony, Brunion, Moritz, Garcia-Ortiz, Alberto, Catthoor, Francky, Milojevic, Dragomir, Komalan, Manu, Cavalcante, Matheus, Riedel, Samuel, Benini, Luca, and Lim, Sung Kyu
- Abstract
Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This article proposes a novel hierarchical physical design flow enabling the building of high-density and commercial-quality two-tier face-to-face-bonded hierarchical 3-D ICs. Complemented with an automated floorplanning solution, the flow allows for system-level physical and architectural exploration of 3-D designs. As a result, we significantly reduce the associated manufacturing cost compared to existing 3-D implementation flows and, for the first time, achieve cost competitiveness against the 2-D reference in large modern designs. Experimental results on complex industrial and open manycore processors demonstrate in two advanced nodes that the proposed flow provides major power, performance, and area/cost (PPAC) improvements of 1.2 - 2.2
$\times $ $\mathrm {20 \%}$ - Published
- 2024
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