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While many new applications prefer manycore processor with a large number of cores, the exploding communications among multiple cores, caches, and off-chip memories is posing a fundamental challenge on manycore designs. Silicon photonics-based interconnection network promises high bandwidth, low latency, and high energy efficiency, and can potentially meet the communication requirements of manycore processors. In this paper, we propose CAMON, a small low-cost silicon photonic chiplet integrated into the manycore processor package. CAMON chiplet can effectively alleviate the communication bottlenecks of manycore processors and improve the energy efficiency of data movement, especially for large-scale systems. We develop a distributed arbitration system, a low-power low-latency optical interface, and an off-chip laser preactivation mechanism for CAMON. The experimental results show that compared with the electrical network, CAMON can improve the full-system performance per energy by $4.6\times $ , speedup the manycore processor by $2.7\times $ , and save the area of the processor die by 3%, in a 512-core system.

Silicon photonic networks are revolutionizing computing systems by improving the energy efficiency, bandwidth, and latency of data movements. Optical modulators, such as microresonators (MRs) and Mach–Zehnder interferometers (MZIs), are the basic building blocks of silicon photonic networks. This paper proposes a SPICE-compatible electro-optical co-simulation model, basic optical switch integration model (BOSIM), to systematically study optical modulators using PN, PIN, and metal–insulator–silicon (MIS) capacitor device technologies. BOSIM holistically models both transient and steady state properties, such as switching speed, power, transmission spectrum, area, and carrier distribution. BOSIM is validated by the measured data from eight research groups and companies. Compared to MRs, BOSIM shows MZIs are fast, with a high extinction ratio and large bandwidth but in the sacrifice of loss, energy, and area. Using a PIN diode over a PN diode can save area, but retain the loss and energy, while an MIS capacitor has the shock response of carrier distribution in a narrow range and is marginalized gradually. For instance, an MZI can achieve a $2.5 {\times }$ bit rate, $6.06{\times }$ extinction ratio, $71.04 {\times }\,\,3$ -dB bandwidth, but costs at least $1.93 {\times }$ passing loss, $1.46 {\times }$ energy consumption, and $16.67 {\times }$ area, compared with MR.

Rack-scale computing systems are promising to undertake the emerging large-scale applications by distributing massive tasks to processing cores. The communication and coordination efficiency of these tasks and resources directly affect the system performance and energy consumption. Silicon photonic interconnects are expected to address the communication and system power consumption challenges imposed on rack-scale systems. However, the control for optical interconnects can cause server performance degradation if not properly designed, especially for the complicated and time-consuming multidomain networks. In this paper, we study the optical interconnects for rack-scale computing systems and propose a new communication flow and control scheme for the efficient coordination of distributed resources. Particularly, we first propose a forward propagation strategy that parallels the path reservation process with the distributed tasks connection setup. Second, we develop a pre-emptive chain feedback (PCF) scheme to optimize multidomain path reservation. The PCF scheme pre-emptively allocates network resources with the help of multicell reservation window and quickly releases resources with a feedback mechanism. This solution increases the network resources utilization and task coordination efficiency while minimizing path reservation overheads. Comparing to the baseline InfiniBand network fabric and handshake scheme, PCF can improve network throughput greatly under uniform and hotspot traffic patterns. Realistic benchmark results show that the PCF scheme on average reduces 52% and 60% energy consumption per unit system performance than InfiniBand and the handshake scheme for a 256-node rack system.

The advancement of silicon photonics promises integrated optical switches to provide high-bandwidth, low-latency, and low-power communications in data centers. An optical switch’s loss limits its scale and affects the energy efficiency of the switch system. In this paper, we present cross-layer optical switch optimization (CLOSO), a cross-layer optimization (CLO) framework, based on not only photonic device models at the physical layer but also optical switch models at the fabric layer. With the proposed framework, optimal losses of optical switches can be evaluated efficiently, and the corresponding losses and design parameters of photonic devices can be obtained. Using CLOSO, we optimize four categories of integrated optical switches, Crossbar, PILOSS, DRAGON, and FODON, and compare them regarding their optimal worst-case loss with variation of the switch scale and data rate of signals. Furthermore, system-level evaluations of the optimized optical switches are performed, demonstrating a significant improvement of energy efficiency from the CLO. For instance, CLOSO helps to reduce the energy consumption of a 64-port DRAGON and FODON to as low as 6 pJ/bit and that of a 128-port DRAGON and FODON to as low as 10 pJ/bit. The investigation of 128-port switches also shows the necessity of adaptive power control on lasers for high-radix integrated optical switches. Through quantitative analyses and comparisons, CLOSO shows the capability of facilitating initial design exploration of optical switches and paves the way to fair evaluations and comparisons of switch systems in data centers.

In recent years, optical interconnection networks have been proposed in order to achieve the ultrahigh bandwidth and low latency requirements for inter/intra-chip communication. In these optical interconection networks, series of basic optical elements are employed. Via these series of optical elements, the intrinsic crosstalk noise is generated. With a large scale of these optical elements, the signal-to-noise ratio (SNR) of an optical interconnect can be reduced by this crosstalk noise. In this paper, we utilize the adaptive power control (APC) to enhance the SNR under the crosstalk noise constraints. APC has been known to save energy and reduce power consumption. We apply this technique in one of the inter/intra-chip optical interconnect called I2CON. A new cluster design, namely the Beam cluster, is also introduced. Results have demonstrated that the APC can help to reduce crosstalk noise, hence, the overall SNR is improved. Comparison results have also indicated the further improvement of SNR in I2CON using Beam cluster when APC is applied.

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.