15 results on '"WANG Chun-yao"'
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2. A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks
3. Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization
4. Majority Logic Circuit Minimization Using Node Addition and Removal
5. LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach
6. A New Necessary Condition for Threshold Function Identification
7. Automatic interconnection rectification for SoC design verification based on the port order fault model
8. An automatic approach to verification pattern generation for SoC design verification using port-order fault model
9. On automatic-verification pattern generation for SoC with port-order fault model
10. LOOPLock: Logic Optimization-Based Cyclic Logic Locking
11. Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments
12. Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays
13. Logic Restructuring Using Node Addition and Removal
14. Fast Node Merging With Don't Cares Using Logic Implications
15. An Implicit Approach to Minimizing Range-Equivalent Circuits
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