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The growing demand on the performance of transparent computing systems requires good cache schemes in order to overcome the prolonged network latency. However, evaluating cache schemes, especially measuring the performance of a transparent computing system with particular cache scheme remains challenging. This is because neither method is available to evaluate the effectiveness and efficiency of the cache schemes in transparent computing, nor the simulator has been developed to measure the system performance under particular cache schemes. In this paper, we propose TranSim, a full-featured, high-performance simulation framework for transparent computing. For the first time, TranSim introduces a methodology to evaluate the performance of multi-level cache hierarchies in transparent computing under different cache configurations and cache replacement policies. TranSim can also demonstrate the behavior and performance of the entire transparent computing system rather than only the cache miss/hit rate. Using TranSim, the system designer can quickly evaluate the effectiveness of cache schemes along with the system performance. We construct several experiments to evaluate the effectiveness and efficiency of TranSim. Results show that TranSim can accurately output the performance of both the cache hierarchy and the entire transparent computing system. [ABSTRACT FROM AUTHOR]

Continuous scaling of process technology increases variations in transistors. The process variations cause large fluctuations in the access times of static random-access memory (SRAM) cells. Caches made of those SRAM cells cannot be accessed within the target clock cycle time, which reduces the yield of processors. Many schemes have been proposed to combat these access time failures in caches. However, these schemes are limited in their coverage and do not scale well at high failure rates. We propose a new level one (L1) cache architecture employing multi-cycle cell access (MCCA) and subarray-level parallel access (SLPA). MCCA eliminates all access-time failures in L1 caches. SLPA minimizes the performance impact of cache bandwidth loss due to MCCA. For further performance improvement, architectural techniques are proposed. Our experimental results show that our proposed L1 cache architecture incurs a performance hit of less than 1.2 percent compared to the conventional cache architecture with no access time failure. Our proposed architecture is not sensitive to access time failure rates and has a low overhead compared with previously proposed competitive schemes. [ABSTRACT FROM AUTHOR]

Privacy protection is the primary concern when RFID applications are deployed in our daily lives. Due to the computational power constraints of passive tags, non-encryption-based singulation protocols have been recently developed, in which wireless jamming is used. However, the existing private tag access protocols without shared secrets rely on impractical physical layer assumptions, and thus they are difficult to deploy. To tackle this issue, we first redesign the architecture of RFID system by dividing an RF reader into two different devices, an RF activator and a trusted shield device (TSD). Then, we propose a novel coding scheme, namely Random Flipping Random Jamming (RFRJ), to protect tags’ content. Unlike the past work, the proposed singulation protocol utilizes only the physical layer techniques that are already implemented. Analyses and simulation results validate our distributed architecture with the RFRJ coding scheme, which defends tags’ privacy against various adversaries including the random guessing attack, correlation attack, ghost-and-leech attack, and eavesdropping. [ABSTRACT FROM AUTHOR]

We propose algorithms for distributing the classifier rules to two ternary content addressable memories (TCAMs) and for incrementally updating the TCAMs. The performance of our scheme is compared against the prevalent scheme of storing classifier rules in a single TCAM in priority order. Our scheme results in an improvement in average lookup speed by up to 49% and an improvement in update performance by up to 3.84 times in terms of the number of TCAM writes. [ABSTRACT FROM AUTHOR]

On-chip photonic waveguides have been proposed as a feasible replacement for the long interconnects that cause speed and power bottlenecks. Along with recent advancements in nanophotonic technologies, we believe that combining on-chip waveguides with high-radix Network on Chip (NoC) topologies is a promising way to improve NoC performance. In this paper, we propose the BufferLess phOtonic ClOs Network (BLOCON) to exploit silicon photonics. We propose a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem, and a methodology to achieve an optimal off-chip laser-power budget. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and on-chip power performance of the compared electrical and photonic NoC architectures over synthetic traffic patterns and SPLASH-2 traces. [ABSTRACT FROM PUBLISHER]